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320
CHAPTER 13 UART
Figure 13.4-2 Communication Flowchart in Mode 1
(Ho
s
t CPU)
S
TART
S
et tr
a
n
s
fer mode to "1".
En
ab
le receive oper
a
tion.
Comm
u
nic
a
te with
a
s
l
a
ve CPU.
Comm
u
nic
a
tion
completed?
NO
NO
YE
S
Di
sab
le receive oper
a
tion.
END
S
et d
a
t
a
us
ed to
s
elect
a
s
l
a
ve CPU in D0 to D7,
s
et "1" in A/D,
a
nd
tr
a
n
s
fer one
b
yte.
S
et "0" in A/D.
Comm
u
nic
a
te
with
a
nother
s
l
a
ve
CPU.
YE
S
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......