374
CHAPTER 16 DMAC (DMA Controller)
[bit23 to bit20] (Reserved): Unused bit
Reading value is fixed to "0000
B
". Writing has no effect.
[bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size setting
Specifies the size for block transfer on the corresponding channel. The value set in these bits specifies the
number of words to transfer for each transfer operation (or, more exactly, the number of times transfer of
the specified word size is repeated). Always set "01
H
" (size 1) when not performing block transfer.
•
Initialized to "0000
B
" when resetting.
•
The read / write is possible.
•
If all-zeros are specified, the block size is set to 16 words.
•
Reading always returns the block size (reload value).
[bit15 to bit00] DTC15 to DTC0 (Dma Terminal Count register) *: Transfer count register
This register stores the number of transfers performed. Each register consists of 16 bits.
Each register has its own reload register. On channels that allow the transfer count register to be reloaded,
the initial value is automatically returned to the register when the transfer completes.
When DMA transfer starts, the data in this register is stored to the counter buffer in the dedicated DMA
transfer counter and the value decremented by one after each transfer. When DMA transfer completes, the
value of the counter buffer is written back to this register and the DMA operation ends. Accordingly, you
cannot use this register to read the specified number of transfers during a DMA operation.
•
Initialized to "00000000_00000000
B
" when resetting.
•
The read / write is possible. Always use halfword or word access to access the DTC register.
•
Reading the register returns the counter value. You cannot read the reload value.
BLK
Function
XXXX
Specifying of block size for corresponding channel
DTC
Function
XXXX
Specifying the number of transfers for corresponding channel
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......