407
CHAPTER 17 FLASH MEMORY
●
Mapping for Access from the ROM writer
Figure 17.1-3 Address Mapping for Access from the ROM Writer
F_FFFF
H
F_C000
H
S
AA9(16 KB)
F_BFFF
H
F_A000
H
S
AA
8
(
8
KB)
F_9FFF
H
F_
8
000
H
S
AA7(
8
KB)
F_7FFF
H
F_0000
H
S
AA6(
3
2 KB)
E_FFFF
H
E_0000
H
S
AA5(64 KB)
D_FFFF
H
D_C000
H
S
AA4(16 KB)
D_BFFF
H
D_A000
H
S
AA
3
(
8
KB)
D_9FFF
H
D_
8
000
H
S
AA2(
8
KB)
D_7FFF
H
D_0000
H
S
AA1(
3
2 KB)
C_FFFF
H
C_0000
H
S
AA0(64 KB)
15
0
Bit po
s
ition
1
0
Byte po
s
ition (when written
b
y the writer)
0
1
When CPU re
a
d
s
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......