477
APPENDIX F Precautions on Handling
■
Notes on Using Debugger
●
Stepping of the RETI instruction
In the environment where interruptions occur frequently during stepping, the RETI is executed repeatedly
for the corresponding interrupt processing routines after the stepping. As the result of it, the main routine
and low-interrupt-level programs are not executed.
To avoid this situation, do not step the RETI instruction. Otherwise, perform debugging by disabling the
interruptions when the debug on the corresponding interrupt routines becomes unnecessary.
●
Operand break
Do not set the access to the areas containing the address of system stack pointer as a target of data event
break.
●
Debugging on unused area of FLASH memory
If debug is performed on the unused area of FLASH memory (where data is 0XFFFF
H
) by mistake, break
will not be accepted. To avoid this situation, the use of address mask function of debugger code event is
recommended to break when an instruction is accessing to the unused area.
●
Power-on debug
When powering off by the power-on debug, be sure to power off under the condition that all the following
three requirements are met.
(1) Time taken to decrease user power supply from 0.9 V
CC
to 0.5 V
CC
is 25 µs or more.
Note: If using two power supplies, V
CC
is external I/O power supply voltage.
(2) CPU operating frequency is 1 MHz or higher.
(3) User program is in execution.
●
Interrupt handler for NMI request (tool)
When ICE is unconnected, to prevent the malfunction caused by noise or other sources affecting DSU pin
to set a flag which is only set by the break request from ICE, add the following programs to the interrupt
handler.
ICE can be used even if this program is added.
Location to add
The following interrupt handler
Interrupt factor
: NMI request (tool)
Interrupt No.
: 13 (decimal), 0D (hexadecimal)
Offset
: 3C8
H
TBR as a default address
: 000FFFC8
H
Additional program
STM
(R0, R1)
LDI
#B00H, R0
; B00
H
is the address of break factor register of DSU.
LDI
#0, R1
STB
R1, @R0
; Clear break factor register.
LDM
(R0, R1)
RETI
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......