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CHAPTER 3 CPU AND CONTROL UNITS
■
Coprocessor Error Trap
A coprocessor error trap occurs if an error occurs when a coprocessor is being used and if a coprocessor
instruction which attempts to operate the coprocessor is executed then.
[Processing]
1. SSP - 4
→
SSP
2. PS
→
(SSP)
3. SSP - 4
→
SSP
4. Next instruction's address
→
(SSP)
5. "0"
→
S-flag
6. (TBR + 3DC
H
)
→
PC
■
Processing of RETI Instruction
The RETI instruction returns control from an EIT service routine.
[Processing]
1. (R15)
→
PC
2. R15 + 4
→
R15
3. (R15)
→
PS
4. R15 + 4
→
R15
The RETI instruction must be executed with the S-flag containing "0".
Note:
The delay slot following a branch instruction has a restriction on EITs.
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......