78
CHAPTER 3 CPU AND CONTROL UNITS
[bit11] SRST (Software ReSeT occurred)
This bit indicates whether a reset (RST) by writing to the SRST bit (software reset) in the STCR register
has occurred.
•
The bit is initialized to "0" immediately after either a reset (INIT) by INIT pin input or a read.
•
A read is possible; a write does not affect the bit value.
[bit10] (reserved bit)
[bit9, bit8] WT1,WT0 (Watchdog interval Time select)
These bits are used to specify the time interval required for the watchdog timer.
The combination of values written to these bits selects the time interval for the watchdog timer from among
the four options listed below.
(
φ
represents the internal base clock period.)
•
These bits are initialized to "00
B
" at a reset (RST)
•
A read is possible; a write is valid only once after a reset (RST). Any further write is invalid.
■
STCR: Standby Control Register
This register controls the operation mode of the device.
The register controls the transition to each of the two standby modes (stop and sleep modes), controls the
pin status and oscillation disable mode during the stop mode, sets the oscillation stabilization wait time, and
issues a software reset.
0
RST by software reset has not occurred.
1
RST by software reset has occurred.
WT1
WT0
Minimum write-to-CTBR interval
required for suppressing watchdog
reset
Time from last 5AH write to CTBR until
watchdog reset
0
0
φ
× 2
16
(Initial value)
φ
× 2
16
to
φ
× 2
17
0
1
φ
× 2
18
φ
× 2
18
to
φ
× 2
19
1
0
φ
× 2
20
φ
× 2
20
to
φ
× 2
21
1
1
φ
× 2
22
φ
× 2
22
to
φ
× 2
23
Bit
7
6
5
4
3
2
1
0
Address: 000481
H
STOP
SLEEP
HIZ
SRST
OS1
OS0
–
OSCD1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (INIT pin)
0
0
1
1
0
0
1
1
Initial value (INIT)
0
0
1
1
×
×
1
1
Initial value (RST)
0
0
×
1
×
×
×
×
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......