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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
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NMI
1. An NMI has the highest level among the user interrupts and cannot be masked.
However, as an exception, when NMI is activated without setting ILM, NMI source is detected but CPU
will not accept the NMI request. At this time, the NMI source will be held until ILM is set to be
accepted by NMI. For this reason, use NMI after resetting and setting ILM value to 16 or higher. Also,
since an internal source flag of NMI cannot be accessed from CPU, keep NMI pin to "H" level after
reset.
2. An NMI is accepted under the following conditions:
Normal state :Falling edge
STOP state :"L" level
3. An NMI can be used to clear stop mode. Inputting the "L" level in the stop state clears the stop state
and causes the oscillation stabilization wait time to start.
The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if an
interrupt for the NMI itself is accepted or reset occurs.
Note that this bit is not readable or writable.
Figure 6.3-4 NMI Request Detector
NMI request
(Stop clearing)
Q
R
(NMI flag)
STOP
0
1
Falling edge
detection
φ
NMI
SX
Clear (RST, interrupt ackno
w
ledge)
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......