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CHAPTER 9 PPG (Programmable Pulse Generator)
9.2
Block Diagram
This section explains the PPG block diagram.
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Block Diagram
Figure 9.2-1 Block Diagram of 8-bit PPG (ch0, ch2, ch4, ch6, ch8, ch10, ch12, ch14)
PRLLn
PPG
output latch
Borro
w
of ch(n+1)
Machine clock divided-by-64
Machine clock divided-by-16
Machine clock divided-by-4
Machine clock
Inversion
Clear
PEN(n+1)
PCNT (do
w
n counter)
PPGCn/TRG
Operation mode
(control)
Data bus for "L" side
Data bus for "H" side
n = 0,2,4,6,8,10,12,14
"H"/"L" selector
"H"/"L" select
PRLHn
Reload
Count clock
selection
S
R Q
PIEn
PUFn
IRQn
PRLBHn
To Port
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......