193
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■
Count Clock Selection
The count clock of counter can select three types of internal clock sources by setting of PWCSR register
(bit7, bit6: CKS1, CKS0).
Selectable count clocks are as shown below.
The clock generated by dividing the machine clock by 4 is selected for the initial value after a reset.
Be sure to select the count clock before the counter starts.
■
Selects Operation Mode
The PWCSR setting is used to select each operation/measurement mode.
•
Operation mode setting:
PWCSR bit2 to bit0: MOD2, MOD1, MOD0
(for example, selecting a pulse width count mode, or determining a
measurement edge)
•
Measurement mode setting:PWCSR bit3: SC
(selecting a single/continuous measurement)
The selection of operation modes by the combination of the mode selecting bits is listed below.
All edge-to-edge measurement-single measurement mode is selected for the initial value after a reset.
Be sure to select the activation mode before the counter starts.
PWCSR
Selecting Internal Count Clock
CKS1, CKS0
00
B
Machine clock 4-divided [initial value]
01
B
Machine clock 16-divided
10
B
Machine clock 32-divided
Operating Mode
SC
MOD2 MOD1
MOD0
Pulse width
measurement
↑
or
↓
to
↑
or
↓
Measurement between all edges
Single measurement: Buffer invalidity
0
0
0
0
Continuous measurement: Buffer effective
1
0
0
0
Measurement at cycle of
dividing frequency
(1-frequency division to
256-frequency division)
Single measurement: Buffer invalidity
0
0
0
1
Continuous measurement: Buffer effective
1
0
0
1
↑
to
↑
Rising-to-rising cycle
measurement
Single measurement: Buffer invalidity
0
0
1
0
Continuous measurement: Buffer effective
1
0
1
0
↑
to
↓
"H" pulse width measurement
Single measurement: Buffer invalidity
0
0
1
1
Continuous measurement: Buffer effective
1
0
1
1
↓
to
↑
"L" pulse width measurement
Single measurement: Buffer invalidity
0
1
0
0
Continuous measurement: Buffer effective
1
1
0
0
↓
to
↓
Falling-to-falling cycle
measurement
Single measurement: Buffer invalidity
0
1
0
1
Continuous measurement: Buffer effective
1
1
0
1
Setting disabled
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......