201
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
■
Note
●
Note on register rewriting
The following bits of the PWCSR register must not be rewritten during an operation. Be sure to rewrite
them before operation is started or after operation is stopped.
[bit7, bit6] CKS1, CKS0: Clock select bit
[bit5, bit4] PIS1, PIS0: Pulse width count input pin select bit
[bit3] SC: Measurement mode (single/continuous) select bit
[bit2, bit1, bit0] MOD2, MOD1, MOD0: Operation mode/measurement edge select bit
The PDIVR register must not be rewritten during an operation. Be sure to rewrite it before operation is
started or after operation is stopped.
●
STRT bit and STOP bit of the PWCSR register
Note that both bits have different meanings in writing and in reading (See "10.3 Register of PWC"). Also,
the read value by a read-modify-write instruction is always "11
B
", regardless of the bit value. For this
reason, note that the bit-processing instructions cannot be used for reading an operation status (the status
must be in operation if it is read).
A bit-processing instruction (such as a bit clear instruction) corresponding to each bit can be used for
writing to the STRT and STOP bits to start/stop the counter.
●
Counter clear
In the pulse width count mode, because a measurement start edge clears a counter, the data which exists in
counter before starting becomes invalided.
●
Minimum input pulse width
The following restrictions apply to the pulse that can be inputted to the pulse width count input pin.
•
Minimum input width: Machine cycle x 4 (
≥
250 ns when machine cycle is 62.5 ns)
•
Maximum input frequency: Clock generated by dividing the machine clock by 4 (
≤
4 MHz when
machine cycle is 16 MHz)
If the pulse which has smaller width/higher frequency than the above is inputted, the operation will be
unpredictable. If there may be such noise on the input signal, remove the noise through a filter outside the
chip, and then input the pulse.
●
Measurement mode at cycle of dividing frequency
Note that the pulse width obtained from the measured result calculation is the average value because the
input pulses are divided in the division cycle measurement mode among the pulse width measurement
modes.
●
Clock select bit
Setting "11
B
" to the (bit7, bit6): CKS1, CKS0: clock select bit of the PWCSR register is prohibited.
●
Reserved bit
The (bit8) of PWCSR register is a reserved bit. When writing to this bit, be sure to set to "0".
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......