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CHAPTER 16 DMAC (DMA Controller)
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Burst Transfer
Figure 16.7-2 Flowchart of Burst Transfer
Initial
BLK=0
DTC=0
DENB=1
DENB=>0
Burst transfer
- Generating interrupt clear at designated transfer number end and generating DMA interrupt.
Load address, transfer
count, and block number
Wait start request
DMA stop
Reload enable
Address operation for
transfer source address access
Address operation for
transfer destination address access
Block number - 1
Transfer count - 1
Write back address, transfer
count, and block number
Clear interrupt
Generating DMA interrupt
Generating interruption clear
At only select peripheral interrupt start source
DMA transfer end
- Starting is possible by all starting factors (option)
- Accessing is possible to all areas
- Setting of block number is possible.
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......