81
CHAPTER 3 CPU AND CONTROL UNITS
•
A read and a write are possible.
Note:
For returning from the STOP mode with OSCD1 = 0 when the main PLL clock is being used as the
clock source, be sure to set the OS1 and OS0 bits in the STCR to a value other than 00
B
to ensure
the lock wait time for the main PLL.
■
TBCR: Timebase Counter Control Register
This register controls timebase timer interrupts.
The register enables timebase timer interrupts, selects the interrupt time interval, and sets optional functions
for reset operation.
Each bit in the timebase counter control register (TBCR) functions as follows:
[bit15] TBIF (TimeBasetimer Interrupt Flag)
This bit serves as the timebase timer interrupt flag.
The flag indicates that the timebase counter has expired the time interval (set by the TBC2 to TBC0 bits, or
bit13 to bit11).
If this bit is set to "1" with the TBIE bit (bit14) enabling interrupts (TBIE = "1"), a timebase timer interrupt
request is generated.
•
The bit is initialized to "0" at a reset (RST).
•
A read and a write are possible. Note, however, that only "0" can be written. An attempt to write "1"
has no effect on the bit value. Note also that reading the bit using a read modify write instruction always
returns "1".
[bit14] TBIE (TimeBasetimer Interrupt Enable)
This bit serves as the timebase timer interrupt request output enable bit.
The bit controls interrupt request output when the timebase counter has expired the time interval. When the
TBIF bit (bit15) is set to "1" with this bit containing "1", a timebase timer interrupt request occurs.
•
The bit is initialized to "0" at a reset (RST).
•
A read and a write are possible.
Bit
15
14
13
12
11
10
9
8
Address: 000482
H
TBIF
TBIE
TBC2
TBC1
TBC0
–
SYNCR SYNCS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (INIT)
0
0
×
×
×
×
0
0
Initial value (RST)
0
0
×
×
×
×
×
×
Clear source
"0" is written by instruction.
Set source
Specified time interval has passed (falling edge of timebase counter output is detected).
0
Disable timebase timer interrupt request output. (Initial value)
1
Enable timebase timer interrupt request output.
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......