background image

6

Q6:

back to top

Can the video input signal be mixed with information by alphablending?

Yes, for example it is possible to put text or graphics on the C-layer alphablended on top of the
video (on W-layer).

Q7:

back to top

There is a I2C interface implemented in Scarlet&Orchid.
On which pins is this interface located ?

The I2C pins of Scarlet are : 184 and 185

For details, see the I2C description of Scarlet !

Q8:

back to top

Scarlet requires 14,32MHz (4* NTSC) input clock.
Is it possible to use another crystal (e.g.14,25MHz) ?
What is the allowed range of deviation (PLL) ?

The 14.25MHz as input clock is OK.
The allowed range of output frequency of PLL is around 195..202kHz.

Q9:

back to top

What is the weight (in grams) of the final Scarlet chip (mass production version) ?

The typical weight of HQFP208 package is 5.17g.
Errors of plus or minus several percent will arise.

Q10:

back to top

Using SH-3 @ 66 Mhz together with Scarlet :
The "XRDY delay time" is specified with t(RDYD)=7ns (max). In the Hitachi SH3-spec there is a value
given for "Wait setup time" = 12ns (min) @ 66MHzoperation frequency. Under these worst case
conditions, the wait line could eventually cause problems. Did your customers had problems with that
? Do you have any recommendations ?

We've assumed the max. frequency of SH3 bus-clock as 50MHz. If customer use higher
frequency, they need to set the software wait to 3 cycle. We are now checking the behavior of
this setting by logic simulation.

Q11:

back to top

Is the load capacitance specified (C=16pF) valid for all ports of Scarlet ?

Yes, all the input load is same.

Summary of Contents for MB86291 Scarlet

Page 1: ...1 FAQ list for MB86291 Scarlet and MB86292 Orchid Fujitsu Microelectronics Europe GmbH History Date Author Version Comment 08 10 2003 AG 1 0 First release ...

Page 2: ... Fujitsu Microelectronics Europe GmbH s entire liability and the customer s exclusive remedy shall be at Fujitsu Microelectronics Europe GmbH s sole discretion either return of the purchase price and the license fee or replacement of the Product or parts thereof if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the cus...

Page 3: ...let Q12 Power consumption figures and temperature of Scarlet Q13 DAC power down mode If only the digital video interface is used for a digital display is it possible for power consumption reduction to save the resistors at Vref AOUTR B G ACOMPB and VRO pin and leave them open or connect them to GND or Vcc 2 5V or 3 3V directly Q14 If CCLK and VI 0 7 at SCARLET are not used what has to be done with...

Page 4: ...will be very high due to all the other operation requirements still fast enough 2D 3D operation is performed by the Rose Scarlet 2 Digital video capture and flexible scaling Video capturing feature was eliminated from Cremson at the very last minute due to the pin count limit Now because of the embedded SDRAM no more external memory interface we have enough pins to assign for digital video input a...

Page 5: ...et Orchid feature an ITU RBT656 YUV 4 2 2 digital video interface An external decoder such as Phillips UAA711x is required to convert the analog video signals to this digital format The data stream will be read in from the Scarlet by the VI port and then written to graphics memory Analog processing upsampling filters etc are part of the external decoder For details see the application note about t...

Page 6: ...p What is the weight in grams of the final Scarlet chip mass production version The typical weight of HQFP208 package is 5 17g Errors of plus or minus several percent will arise Q10 back to top Using SH 3 66 Mhz together with Scarlet The XRDY delay time is specified with t RDYD 7ns max In the Hitachi SH3 spec there is a value given for Wait setup time 12ns min 66MHzoperation frequency Under these ...

Page 7: ...VCC pin 2 5V 25mA VDDE pin 3 3V 2 2 Estimates The power consumption 1 585W A rise rate of package 16 degree W The temperature of package 25 Ta 1 585 16 50 36 degree 85 Ta 1 585 16 110 36 degree Q13 back to top DAC power down mode If only the digital video interface is used for a digital display is it possible for power consumption reduction to save the resistors at Vref AOUTR B G ACOMPB and VRO pi...

Page 8: ...MHz CCLK freq Q17 back to top How much is the decrease of drawing performance while using AAF Feature Anti aliasing line s performance is 30 40 of normal line s performance Q18 back to top What can I do to make the Orchid chroma key function work on the PCI board Unfortunately there are some hardware bugs on the Orchid board which have to be fixed 1 Polarity of clamp pulse positive pulse must be g...

Page 9: ...k to top How can I switch on off the LEDs on the PCI board for testing LEDs are memory mapped in the IO space But the current map driver mapdrv dll can not access the LED register which is mapped FPGA on the PCI board because this PCI map driver can access only 64MB The LED register is mapped 0x04001000 area So if you want to access the LED register please use the old map driver uty_cremson dll sa...

Page 10: ...R reg DWORD HostBase 0x0000fffc reg 0x003f3802 SDRAM Settings IMASK reg DWORD HostBase 0x00000024 reg 0x0000001f 1f all Interrupts to Host CPU disabled Q22 back to top using the Orchid MB86292 we want to use a single 32 bit SDRAM from Micron MT48LC4M32B2 Do the unused Data lines MD32 MD54 and MDQM4 7 need a pull up resistor to have a known state or can I leave them open Please connect XRGBEN to Lo...

Page 11: ...16MByte graphics memory the banks are mapped like the below 0x00000000 0x001fffff bank 0 0x00200000 0x003fffff bank 1 0x00400000 0x005fffff bank 2 0x00600000 0x007fffff bank 3 Then if you map each layer as the below it is the bank interleave 0x00000000 0x001fffff bank 0 B layer 0x00200000 0x003fffff bank 1 M layer 0x00400000 0x005fffff bank 2 W layer 0x00600000 0x007fffff bank 3 C Layer Q26 back t...

Reviews: