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CHAPTER 7 MODE SETTING
7.4
External Memory Access
This section contains block diagrams about external memory access, the
configuration and functions of registers, and operation of external memory access.
■
I/O signal pins for external memory access
For accessing external memory and peripheral devices, the F
2
MC-16LX supplies the following
address, data, and control signals:
•
CLK (P57): Outputs the machine cycle clock (KBP)
•
RDY (P56): External ready input pin
•
HAK (P55): Hold acknowledge output pin
•
HRQ (P54): Hold request input pin
•
WRH (P53): Write signal for the high-order 8 bits on the data bus
•
WRL (P52): Write signal for the low-order 8 bits on the data bus
•
RD (P51): Read signal
•
ALE (P50): Address latch enable signal (effective in the multiplex mode)
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Block diagram
Figure 7.4-1 is a block diagram of the external bus pin control circuit.
Figure 7.4-1 Block diagram of external bus pin control circuit
Internal address
bus
Internal data
bus
Access control
Access control
Address control
Data control
P0 direction
P0 data
P0
P5
P0
P1
P2
P3
P4
P5
Summary of Contents for MB90480 Series
Page 2: ......
Page 4: ......
Page 10: ...vi ...
Page 128: ...106 CHAPTER 4 RESET ...
Page 174: ...152 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 198: ...176 CHAPTER 7 MODE SETTING ...
Page 220: ...198 CHAPTER 9 TIMEBASE TIMER ...
Page 238: ...216 CHAPTER 11 WATCH TIMER ...
Page 280: ...258 CHAPTER 12 16 BIT INPUT OUTPUT TIMER ...
Page 406: ...384 CHAPTER 17 8 10 BIT A D CONVERTER ...
Page 478: ...456 CHAPTER 20 CHIP SELECTION FACILITY ...
Page 494: ...472 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ...
Page 498: ...476 CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ...
Page 526: ...504 CHAPTER 23 2M 3M BIT FLASH MEMORY ...
Page 536: ...514 CHAPTER 24 EXAMPLES OF MB90F481B MB90F482B MB90F488B MB90F489B SERIAL PROGRAMMING ...
Page 570: ...548 CHAPTER 25 PWC TIMER ONLY MB90485 SERIES ...
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