xviii
437
❍
Clock setting in synchronous transfer is added
438 to 444
The whole description across 19.7 Program Example of UART is changed.
452
The figure of bit configuration in
■
Chip selection control register (CSCR) is changed.
(* : The initial value of this bit is "1" or "0". The value depends on the mode pins (MD2, MD1, D0 pins). is
added.)
474
■
Registers of the ROM mirror function selection module is changed.
(The figure of bit configuration is changed.)
475
■
ROMM (ROM mirror function selection register) is changed.
(The figure of bit configuration is changed.)
[bit9] MS is changed.
(Note: is added)
478
■
Features of the 2M/3M bit flash memory is changed.
(The description of
•
3M: 384K words x 8 bits/192K words x 16 bits (16K + 8K + 8K + 32K + 64K + 64K +
64K + 64K + 64K) sector configuration is added.)
479
Figure 23.2-1 Sector Configuration of 2M/3M Bit Flash Memory is changed.
501
■
Suspending sector erasure for the flash memory is changed.
(If a sector erase suspend command is entered during the sector erase wait time, sector erase wait ends imme-
diately, the erase operation is interrupted, and the operational state changes to erase stop. If a erase suspend
command is entered during a sector erase operation after the sector erase wait time, the system enters the
erase suspend mode after 15
μ
s have elapsed or earlier.
→
If a erase suspend command is entered during a
sector erase operation after the sector erase wait time, the system enters the erase suspend mode after 20
μ
s
have elapsed or earlier. Please execute the sector erase stop command after sector erase command or sector
erase resume command issuing and 20
μ
s or more.)
503
Table 23.7-1 Flash Security Bit Address is changed.
(Flash memory size and Security bit address of MB90F489B are added)
506
■
Basic Configuration of Serial Programming Connection with MB90F481B/MB90F482B/MB90F488B/
MB90F489B is changed.
(It is possible to write it by selecting either of the program that operates by the single chip mode or the inter-
nal ROM external ROM bus mode. is added.)
507
Table 24.1-1 Function of pins is changed.
527, 528
25.4 Interrupt of PWC Timer is added
563
[bit12] MSS: Master Slave Select is changed.
(Note: is added)
572, 573
27.4 Interrupt of I
2
C Interface is added
579
Table A-1 Relationship among address #1, address #2, and address #3 by product type is changed.
(Contents of the table is changed.)
(*1 and *2 are added.)
580
Figure A-2 MB90F489B memory map is added
589
Table C-1 Relationship between interrupt sources and interrupt vector/interrupt control registers is changed.
625
Table D.8-17 6 Accumulator operation instructions (byte, word) is changed.
(SWAPW / XCHW A,T
→
SWAPW)
Page
Changes (For details, refer to main body.)
Summary of Contents for MB90480 Series
Page 2: ......
Page 4: ......
Page 10: ...vi ...
Page 128: ...106 CHAPTER 4 RESET ...
Page 174: ...152 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 198: ...176 CHAPTER 7 MODE SETTING ...
Page 220: ...198 CHAPTER 9 TIMEBASE TIMER ...
Page 238: ...216 CHAPTER 11 WATCH TIMER ...
Page 280: ...258 CHAPTER 12 16 BIT INPUT OUTPUT TIMER ...
Page 406: ...384 CHAPTER 17 8 10 BIT A D CONVERTER ...
Page 478: ...456 CHAPTER 20 CHIP SELECTION FACILITY ...
Page 494: ...472 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ...
Page 498: ...476 CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ...
Page 526: ...504 CHAPTER 23 2M 3M BIT FLASH MEMORY ...
Page 536: ...514 CHAPTER 24 EXAMPLES OF MB90F481B MB90F482B MB90F488B MB90F489B SERIAL PROGRAMMING ...
Page 570: ...548 CHAPTER 25 PWC TIMER ONLY MB90485 SERIES ...
Page 688: ......