222
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
■
Block diagram of pin related to 16-bit input/output timer
Figure 12.2-5 Block diagram of pin related to 16-bit input/output timer
PDR Re
a
d
PDR Write
Port d
a
t
a
regi
s
ter (PDR)
DDR Write
DDR Re
a
d
(DDR)
Peripher
a
l f
u
nction o
u
tp
u
t
(OUT0 to 5)
N-ch
P-ch
S
t
a
nd
b
y control:
S
top mode (
S
PL=1), time
bas
e timer mode (
S
PL=1), w
a
tch mode (
S
PL=1)
(IN0/IN1)
(P46/P47 only)
O
u
tp
u
t l
a
tch
Peripher
a
l
f
u
nction inp
u
t
Peripher
a
l f
u
nction o
u
tp
u
t en
ab
le
Open dr
a
in control
s
ign
a
l
Pin
Inter
n
a
l d
a
t
a
bu
s
Port direction regi
s
ter
Direction l
a
tch
S
t
a
nd
b
y control (
S
PL=1)
Summary of Contents for MB90480 Series
Page 2: ......
Page 4: ......
Page 10: ...vi ...
Page 128: ...106 CHAPTER 4 RESET ...
Page 174: ...152 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 198: ...176 CHAPTER 7 MODE SETTING ...
Page 220: ...198 CHAPTER 9 TIMEBASE TIMER ...
Page 238: ...216 CHAPTER 11 WATCH TIMER ...
Page 280: ...258 CHAPTER 12 16 BIT INPUT OUTPUT TIMER ...
Page 406: ...384 CHAPTER 17 8 10 BIT A D CONVERTER ...
Page 478: ...456 CHAPTER 20 CHIP SELECTION FACILITY ...
Page 494: ...472 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ...
Page 498: ...476 CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ...
Page 526: ...504 CHAPTER 23 2M 3M BIT FLASH MEMORY ...
Page 536: ...514 CHAPTER 24 EXAMPLES OF MB90F481B MB90F482B MB90F488B MB90F489B SERIAL PROGRAMMING ...
Page 570: ...548 CHAPTER 25 PWC TIMER ONLY MB90485 SERIES ...
Page 688: ......