481
CHAPTER 23 2M/3M BIT FLASH MEMORY
[bit5] WE: Write Enable
This bit is a write-enable bit for the flash memory area.
If this bit is "1", a command sequence that targets banks FC to FF (refer to Section "23.4
Method for Starting the Flash Memory's Automatic Algorithm") will result in a write operation
in the flash memory area. If this bit is "0", no write/erase signals are generated. This bit is
used for initiating write/erase commands with respect to the flash memory.
In order to prevent accidental writing of any data to the flash memory, Fujitsu recommends
always setting this bit to "0" whenever no write/erase operations are to be executed.
[bit4] RDY: ReadDY
This bit is used to allow flash memory write/erase operations to be performed.
If this bit is "0", write/erase operations with respect to the flash memory are not allowed.
However, the command of read/reset and sector erase suspend can be accepted in this
state.
[bit3] Reserved bit
This bit is reserved. Always set this bit to "0" for ordinary use.
[bit1] Reserved bit
This bit is reserved. Always set this bit to "0" for ordinary use.
[bit2, bit0] LPM1, LPM0: Low Power Mode
These bits are used to control flash memory power consumption. If these bits are set to "00",
flash memory operations are performed normally. If these bits are set to "01", "10" or "11",
however, access to flash memory according to the select signal will be performed in low
power consumption mode. In this case, access time increases significantly compared to
access with LPM = "00", and memory access will be disabled during high-speed operation of
the CPU. To use this mode, use a CPU with a frequency 4 MHz, 8 MHz, or 10 MHz.
Note:
For a CPU operation frequency of 10 MHz or higher, always use normal mode.
0
Flash memory write/erase prohibited
1
Flash memory write/erase allowed
0
Write/erase operation in progress
1
End of write/erase operation (next data write/erase operation is enabled)
LPM1 LPM0
Power consumption mode
0
0
Normal power consumption mode
0
1
Power saving mode (operation with an internal operation frequency of 4MHz)
1
0
Power saving mode (operation with an internal operation frequency of 8MHz)
1
1
Power saving mode (operation with an internal operation frequency of 10MHz)
Summary of Contents for MB90480 Series
Page 2: ......
Page 4: ......
Page 10: ...vi ...
Page 128: ...106 CHAPTER 4 RESET ...
Page 174: ...152 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 198: ...176 CHAPTER 7 MODE SETTING ...
Page 220: ...198 CHAPTER 9 TIMEBASE TIMER ...
Page 238: ...216 CHAPTER 11 WATCH TIMER ...
Page 280: ...258 CHAPTER 12 16 BIT INPUT OUTPUT TIMER ...
Page 406: ...384 CHAPTER 17 8 10 BIT A D CONVERTER ...
Page 478: ...456 CHAPTER 20 CHIP SELECTION FACILITY ...
Page 494: ...472 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ...
Page 498: ...476 CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ...
Page 526: ...504 CHAPTER 23 2M 3M BIT FLASH MEMORY ...
Page 536: ...514 CHAPTER 24 EXAMPLES OF MB90F481B MB90F482B MB90F488B MB90F489B SERIAL PROGRAMMING ...
Page 570: ...548 CHAPTER 25 PWC TIMER ONLY MB90485 SERIES ...
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