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662
SDCR
Communication prescaler control register0/1
................................... 395
SDR
Serial data register 0/1 (SDR0/SDR1)
Sector
Sector configuration
............................................ 479
Sector erase
Chip/sector erase operation
................................... 489
Erasing arbitrary data in the flash memory
(sector erase)
......................................... 499
Sector erase operation
.......................................... 493
Sector erase suspend
............................ 490, 491, 493
State transitions of sector erase timer flag (DQ3)
Write/chip sector erase operation
............................ 492
Write/chip sector erase operations
........................... 491
Sector erasure
Procedure for sector erasure
.................................. 499
Resuming the sector erasure of flash memory
Suspending sector erasure for the flash memory
Security
Cancel of security
............................................... 503
Operation in security permission
............................ 503
Setting of security
............................................... 503
Serial
Serial input/output register (SIDR/SODR)
Serial status register (SSR)
.................................... 417
Serial control
Serial control register (SCR)
.................................. 414
Serial data
Operation during serial data transfer
Serial data register 0/1 (SDR0/SDR1)
Serial I/O
Operational states of serial I/O units
Serial mode
Serial mode control status register0/1
(SMCS0/1)
........................................... 390
Serial mode register (SMR)
................................... 412
Serial Programming
Examples of Serial Programming Connections
Setting
Setting and Operating State
................................... 468
Setting bit
Bus mode setting bit (M1,M0)
............................... 157
Setting bits of different modes (S1,S0)
Shift clock
External shift clock mode
..................................... 398
Internal shift clock mode
...................................... 398
Shift operation
Start/Stop timing and input/output timing of shift
operation
.............................................. 401
SIDR
Serial input/output register (SIDR/SODR)
Single chip mode
Pin state in single chip mode
.................................. 143
Single mode
Example of
μ
DMAC start in single mode
Single-Chip
Example of Connection in Single-Chip Mode (When Using
.......................... 510
Slave
Communication procedure of master/slave communication
function
............................................... 435
Connection between CPUs in master/slave
communication
..................................... 434
Register settings in master/slave communication
Sleep mode
Canceling the sleep mode
..................................... 134
Change to sleep mode
.......................................... 133
SLP
Priority of STP,SLP,and TMD bits
SMCS
Serial mode control status register0/1
........................................... 390
SMR
Serial mode register (SMR)
................................... 412
SODR
Serial input/output register (SIDR/SODR)
Software
Notes on software interrupt
..................................... 66
Return from software interrupt
................................. 65
Software interrupt operation
.................................... 66
Start of software interrupt
....................................... 65
SPB
Bank select prefix (PCB,DTB,ADB,SPB)
SSP
User stack pointer (USP) and system stack pointer
.................................................... 32
SSR
Serial status register (SSR)
................................... 417
Stack
Stack area
........................................................... 91
Stack operation
Stack operation during return from interrupt
processing
.............................................. 90
Stack operation when interrupt processing starts
Standby
Change to standby mode and interrupts
Operational states in standby mode
Standby mode
.................................................... 125
Standby mode
Cancellation of standby mode by interrupt
Notes on Accessing the Low-Power Consumption Mode
Control Register (LPMCR) to Enter the Standby
Mode
.................................................. 150
Start
Start condition
................................................... 574
State transition
State transition diagram
........................................ 141
State transitions during count operation
Stop
Stop
................................................................ 536
Stop condition
Summary of Contents for MB90480 Series
Page 2: ......
Page 4: ......
Page 10: ...vi ...
Page 128: ...106 CHAPTER 4 RESET ...
Page 174: ...152 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 198: ...176 CHAPTER 7 MODE SETTING ...
Page 220: ...198 CHAPTER 9 TIMEBASE TIMER ...
Page 238: ...216 CHAPTER 11 WATCH TIMER ...
Page 280: ...258 CHAPTER 12 16 BIT INPUT OUTPUT TIMER ...
Page 406: ...384 CHAPTER 17 8 10 BIT A D CONVERTER ...
Page 478: ...456 CHAPTER 20 CHIP SELECTION FACILITY ...
Page 494: ...472 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ...
Page 498: ...476 CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ...
Page 526: ...504 CHAPTER 23 2M 3M BIT FLASH MEMORY ...
Page 536: ...514 CHAPTER 24 EXAMPLES OF MB90F481B MB90F482B MB90F488B MB90F489B SERIAL PROGRAMMING ...
Page 570: ...548 CHAPTER 25 PWC TIMER ONLY MB90485 SERIES ...
Page 688: ......