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CHAPTER 18 EXPANDED I/O SERIAL INTERFACE
18.4
Interrupt of Expanded I/O Serial Interface
The interrupt of the expanded I/O serial interface occurs when the data transfer is
terminated.
The interrupt of the expanded I/O serial interface can activate the DMA transfer and
extended intelligent I/O service (EI
2
OS).
■
Interrupt of expanded I/O serial interface
The following table shows the interrupt control bit and interrupt source of the expanded I/O
serial interface.
■
Interrupt source related to expanded I/O serial interface
The interrupt of the expanded I/O serial interface occurs when the data transfer is terminated.
The interrupt request to CPU is executed when the SIE (bit12) flag in the serial mode control
status register (SMCS) is set and SIE (bit11): interrupt enable is "1".
■
Interrupt of expanded I/O serial interface, DMA transfer, and EI
2
OS
Table 18.4-1 shows the relationship between the interrupt source, interrupt vector, and interrupt
control register other than software interrupt.
Note:
If there are two interrupt sources in the same interrupt number, resource clears both interrupt
request flags. Therefore, when one of two sources uses the EI
2
OS/
μ
DMAC function, the other
interrupt function cannot use. The interrupt request enable bit of the relevant resource is set to 0 to
execute the software polling processing.
■
Correspondence to DMA transfer and EI
2
OS function
The expanded I/O serial interface corresponds to the DMA transfer function and EI
2
OS function.
When the DMA or EI
2
OS function is used, it is necessary to disable other interrupt that shares
the interrupt control register (ICR).
Interrupt of serial I/O
Interrupt request flag
SMCS0:SIR (bit11) ch.0
SMCS1:SIR (bit11) ch.1
Interrupt request output
enable bit
SMCS0:SIE (bit12) ch.0
SMCS1:SIE (bit12) ch.1
Interrupt generation source
Terminate transfer of serial data
Table 18.4-1 Interrupt source, interrupt vector, and interrupt control register
Interrupt source
EI
2
OS
clear
μ
DMAC
channel
number
Interrupt vector
Interrupt control register
Number
Address
Number
Address
SIO1
❍
13
#37
FFFF68
H
ICR13
0000BD
H
SIO2
❍
14
#38
FFFF64
H
❍
:
Interrupt request flag is cleared.
Summary of Contents for MB90480 Series
Page 2: ......
Page 4: ......
Page 10: ...vi ...
Page 128: ...106 CHAPTER 4 RESET ...
Page 174: ...152 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 198: ...176 CHAPTER 7 MODE SETTING ...
Page 220: ...198 CHAPTER 9 TIMEBASE TIMER ...
Page 238: ...216 CHAPTER 11 WATCH TIMER ...
Page 280: ...258 CHAPTER 12 16 BIT INPUT OUTPUT TIMER ...
Page 406: ...384 CHAPTER 17 8 10 BIT A D CONVERTER ...
Page 478: ...456 CHAPTER 20 CHIP SELECTION FACILITY ...
Page 494: ...472 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ...
Page 498: ...476 CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ...
Page 526: ...504 CHAPTER 23 2M 3M BIT FLASH MEMORY ...
Page 536: ...514 CHAPTER 24 EXAMPLES OF MB90F481B MB90F482B MB90F488B MB90F489B SERIAL PROGRAMMING ...
Page 570: ...548 CHAPTER 25 PWC TIMER ONLY MB90485 SERIES ...
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