569
CHAPTER 27 I
2
C INTERFACE (ONLY MB90485 SERIES)
Note:
The "+ 4" cycle in the formula reflects the minimum overhead for checking whether the output level
of the SCL pin has changed. If the rising edge of the SCL pin is delayed or a slave device delays
the clock, the overhead increases. Do not set the serial clock frequency to 100 kHz or more.
Table 27.3-1 Serial clock frequency settings
m
CS4
CS3
n
CS2
CS1
CS0
5
0
0
4
0
0
0
6
0
1
8
0
0
1
7
1
0
16
0
1
0
8
1
1
32
0
1
1
64
1
0
0
128
1
0
1
256
1
1
0
512
1
1
1
Summary of Contents for MB90480 Series
Page 2: ......
Page 4: ......
Page 10: ...vi ...
Page 128: ...106 CHAPTER 4 RESET ...
Page 174: ...152 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 198: ...176 CHAPTER 7 MODE SETTING ...
Page 220: ...198 CHAPTER 9 TIMEBASE TIMER ...
Page 238: ...216 CHAPTER 11 WATCH TIMER ...
Page 280: ...258 CHAPTER 12 16 BIT INPUT OUTPUT TIMER ...
Page 406: ...384 CHAPTER 17 8 10 BIT A D CONVERTER ...
Page 478: ...456 CHAPTER 20 CHIP SELECTION FACILITY ...
Page 494: ...472 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ...
Page 498: ...476 CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ...
Page 526: ...504 CHAPTER 23 2M 3M BIT FLASH MEMORY ...
Page 536: ...514 CHAPTER 24 EXAMPLES OF MB90F481B MB90F482B MB90F488B MB90F489B SERIAL PROGRAMMING ...
Page 570: ...548 CHAPTER 25 PWC TIMER ONLY MB90485 SERIES ...
Page 688: ......