SCSI BUS
7-38 C156-E228-02EN
Data Release Delay + Bus Settle Delay (Min)
Deskew Delay (Max)
Data Release Delay (Max)
Figure 7.18
Switching direction of transfer over the data bus
7.6.11 Time monitoring feature
The ODD has a time monitoring feature for the SCSI bus to prevent hang-up of
the SCSI bus in the case that the TARG cannot receive a response from the INIT
in the RESELECTION or INFORMATION TRANSFER phase.
(1) Time monitoring in RESELECTION phase
The ODD monitors the time of the response (BSY signal) from the INIT in the
RESELECTION phase. When the INIT does not send the BSY signal within a
specified period, the ODD executes the timeout process (see Subsection 7.6.4) to
free the SCSI bus and then executes the retry process (see Section 6.1) of the
RESELECTION phase in "MCD3130SS, MCE3130SS, MCK3130SS,
MCM3064SS, MCM3130SS Optical Disk Drives SCSI Logical Interface
Specifications."
(2) Time monitoring in INFORMATION TRANSFER phase
The ODD monitors the timing of the ACK signal against the REQ signal in the
INFORMATION TRANSFER phase. Time monitoring is executed during the
following period:
•
COMMAND, STATUS, or MESSAGE phase:
Time taken from the moment of sending the REQ signal of the first byte to the
moment of completing the reception of the ACK signal of the last byte of the
phase.
Summary of Contents for MCM3064SS
Page 1: ...C156 E228 02EN MCM3064SS MCM3130SS MCP3064SS MCP3130SS OPTICAL DISK DRIVES PRODUCT MANUAL ...
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Page 42: ...Specifications 2 12 C156 E228 02EN Figure 2 3 Example of alternate processing ...
Page 47: ...3 2 Mounting Requirements C156 E228 02EN 3 5 Figure 3 2 Outer dimensions 1 of 2 ...
Page 49: ...3 2 Mounting Requirements C156 E228 02EN 3 7 Figure 3 3 Outer dimensions 1 of 3 ...
Page 51: ...3 2 Mounting Requirements C156 E228 02EN 3 9 Figure 3 3 Outer dimensions 3 of 3 ...
Page 82: ...Installation 4 16 C156 E228 02EN Figure 4 6 SCSI connection check ...
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Page 148: ...SCSI BUS 7 46 C156 E228 02EN Figure 7 21 Bus phase sequence 1 of 2 ...
Page 149: ...7 8 Bus Sequence C156 E228 02EN 7 47 Figure 7 21 Bus phase sequence 2 of 2 ...
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