7.7 Bus Conditions
C156-E228-02EN 7-43
All SCSI devices must deactivate all the bus signals except RST signals and
release the bus within 800 ns (Bus Clear Delay) after the RST signal becomes true.
After the RESET condition, the SCSI bus must enter the BUS FREE phase.
Figure 7.20 shows the RESET condition.
The following are the ODD operations when the RESET condition is detected.
1) All commands including those being executed and those in a stack are
cleared.
2) The reserve status of the disk drive is reset.
3) The operation mode set by a message or the command is initialized as when
power is turned on.
The current value in the parameter set by a MODE SELECT command is
initialized to the saved value last established. If the value is not saved, it is
initialized to the default value.
Parameters defined for synchronous transfer between the ODD and SCSI
device is cleared. The mode defined for data transfer among all SCSI devices
is initialized to asynchronous mode.
4) The UNIT ATTENTION condition is generated for all SCSI devices.
5) The sense data is no longer retained and is cleared.
6) All data read into the data buffer in advance by the read-ahead cache feature
is invalidated.
1. The ODD does not generate a RESET condition.
2. The ODD provides only the "hard" RESET condition specified
by the SCSI standard.
3. Reset Hold Time is specified to guarantee that any SCSI device
can recognize the occurrence the RESET condition. On the
ODD, even if the pulse width is less than 25
µ
s, the RESET
condition is effective.
Summary of Contents for MCM3064SS
Page 1: ...C156 E228 02EN MCM3064SS MCM3130SS MCP3064SS MCP3130SS OPTICAL DISK DRIVES PRODUCT MANUAL ...
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Page 42: ...Specifications 2 12 C156 E228 02EN Figure 2 3 Example of alternate processing ...
Page 47: ...3 2 Mounting Requirements C156 E228 02EN 3 5 Figure 3 2 Outer dimensions 1 of 2 ...
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Page 82: ...Installation 4 16 C156 E228 02EN Figure 4 6 SCSI connection check ...
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Page 148: ...SCSI BUS 7 46 C156 E228 02EN Figure 7 21 Bus phase sequence 1 of 2 ...
Page 149: ...7 8 Bus Sequence C156 E228 02EN 7 47 Figure 7 21 Bus phase sequence 2 of 2 ...
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