C141-E077-01EN
5 - 89
Table 5.16 Ultra DMA data burst timing requirements (2 of 2)
NAME
MODE 0
(in ns)
MODE 1
(in ns)
MODE 2
(in ns)
MODE 3
(in ns)
MODE 4
(in ns)
COMMENT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
(see Notes 1 and 2)
t
ZIORDY
0
0
0
0
0
Minimum time before driving
IORDY
t
ACK
20
20
20
20
20
Setup and hold times for DMACK-
(before assertion or negation)
t
SS
50
50
50
50
50
Time from STROBE edge to
negation of DMARQ or assertion of
STOP (when sender terminates a
burst)
Notes:
1)
Unless otherwise specified, timing parameters shall be measured at the connector of the sender or receiver to which the parameter
applies (see Note 5 for exceptions). For example, the sender shall stop generating STROBE edges t
RFS
after the negation of
DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the sender.
2)
All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
3)
t
UI
, t
MLI
and t
LI
indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for
the other agent to respond with a signal before proceeding. t
UI
is an unlimited interlock that has no maximum time value. t
MLI
is a
limited time-out that has a defined minimum. t
LI
is a limited time-out that has a defined maximum.
4)
Special cabling shall be required in order to meet data setup (t
DS
) and data hold (t
DH
) times in modes 3 and 4.
5)
Timing for t
DVS
and t
DVH
shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.
Summary of Contents for MPE3064AT
Page 1: ...C141 E077 02EN MPE3xxxAT DISK DRIVES PRODUCT MANUAL ...
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Page 31: ...C141 E077 02EN 3 2 Figure 3 1 Dimensions ...
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Page 51: ...C141 E077 01EN 4 6 Figure 4 2 MPE3xxxAT Block diagram ...
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