Appendix B
Components
B-7
■
In case of SPARC64 VI processor:
2.28 GHz, L2 cache 5M bytes/2.4 GHz, L2 cache 6M bytes
■
In case of SPARC64 VII processor:
2.52 GHz, L2 cache 6M bytes/2.88 GHz, L2 cache 6M bytes
■
In case of SPARC64 VII+ processor:
3.0 GHz, L2 cache 12M bytes
Note –
To make maximum use of the 12M bytes L2 cache memory with SPARC64 VII+
processors, it is necessary to use a certain type of CMU (CMU_C) and mount the CPU
modules which consist entirely of the SPARC64 VII+ processors. If the CPU modules of
different frequencies are mixed on CMU_C, the usable L2 cache memory is limited to 6M
bytes. Also, if you use other types of CMU (CMU_A or CMU_B) and mount the CPU
modules which consist entirely of the SPARC64 VII+ processor, the usable L2 cache
memory is limited to 6M bytes.
■
For the bus connecting CPU and SC, a high-speed link is used.
■
The CPU module has a label bearing the printed component number and manufacture's
serial number.
Summary of Contents for SPARC Enterprise M8000
Page 4: ......
Page 15: ...Contents xv Index Index 1 ...
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Page 27: ...Chapter 1 Safety and Tools 1 5 M9000 Server Front View ...
Page 29: ...Chapter 1 Safety and Tools 1 7 Power Supply Unit PSU ...
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Page 205: ...Chapter 7 I O Unit IOU Replacement 7 13 FIGURE 7 8 Removing the IOU Front of M9000 1 1 2 3 ...
Page 227: ...Chapter 8 FAN Unit Replacement 8 11 FIGURE 8 9 Removing the FAN Unit Rear of M8000 1 2 ...
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Page 409: ...Chapter 20 Backplane Replacement 20 29 FIGURE 20 16 Removing the FANBP Rear of the M8000 ...
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Page 439: ...Chapter 23 Switch Backplane Replacement 23 7 FIGURE 23 4 Removing the SWBP Rear of the M8000 ...
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