5-110
B90 Low Impedance Bus Differential System
GE Multilin
5.4 FLEXLOGIC
5 SETTINGS
5
The equation for virtual output 4 is:
[85] Virt Op 4 On
[86] Virt Op 1 On
[87] Virt Op 2 On
[88] Virt Ip 1 On
[89] DIG ELEM 1 PKP
[90] XOR(2)
[91] Virt Op 3 On
[92] OR(4)
[93] LATCH (S,R)
[94] Virt Op 3 On
[95] TIMER 1
[96] Cont Ip H1c On
[97] OR(3)
[98] TIMER 2
[99] = Virt Op 4
It is now possible to check that the selection of parameters will produce the required logic by converting the set of parame-
ters into a logic diagram. The result of this process is shown below, which is compared to the logic for virtual output 4 dia-
gram as a check.
Figure 5–43: FLEXLOGIC EQUATION FOR VIRTUAL OUTPUT 4
7.
Now write the complete FlexLogic expression required to implement the logic, making an effort to assemble the equa-
tion in an order where Virtual Outputs that will be used as inputs to operators are created before needed. In cases
where a lot of processing is required to perform logic, this may be difficult to achieve, but in most cases will not cause
problems as all logic is calculated at least four times per power frequency cycle. The possibility of a problem caused by
sequential processing emphasizes the necessity to test the performance of FlexLogic before it is placed in service.
In the following equation, virtual output 3 is used as an input to both latch 1 and timer 1 as arranged in the order shown
below:
DIG ELEM 2 OP
Cont Ip H1c On
NOT
AND(2)
FLEXLOGIC ENTRY n:
Virt Op 3 On
FLEXLOGIC ENTRY n:
OR (4)
FLEXLOGIC ENTRY n:
LATCH (S,R)
91
92
93
FLEXLOGIC ENTRY n:
DIG ELEM 1 PKP
FLEXLOGIC ENTRY n:
XOR
89
90
XOR
FLEXLOGIC ENTRY n:
Virt Op 1 On
FLEXLOGIC ENTRY n:
Virt Op 2 On
FLEXLOGIC ENTRY n:
Virt Ip 1 On
86
87
88
FLEXLOGIC ENTRY n:
Virt Op 4 On
85
FLEXLOGIC ENTRY n:
=Virt Op 4
99
FLEXLOGIC ENTRY n:
OR (3)
FLEXLOGIC ENTRY n:
TIMER 2
96
97
98
FLEXLOGIC ENTRY n:
Virt Op 3 On
FLEXLOGIC ENTRY n:
TIMER 1
94
95
LATCH
Reset
Set
OR
OR
T1
T2
VIRTUAL
OUTPUT 4
827031A2.VSD
FLEXLOGIC ENTRY n:
Cont Ip H1c On
Summary of Contents for B90
Page 10: ...x B90 Low Impedance Bus Differential System GE Multilin TABLE OF CONTENTS ...
Page 284: ...5 166 B90 Low Impedance Bus Differential System GE Multilin 5 8 TESTING 5 SETTINGS 5 ...
Page 334: ...10 8 B90 Low Impedance Bus Differential System GE Multilin 10 2 BATTERIES 10 MAINTENANCE 10 ...
Page 338: ...A 4 B90 Low Impedance Bus Differential System GE Multilin A 1 PARAMETER LISTS APPENDIX A A ...
Page 460: ...C 30 B90 Low Impedance Bus Differential System GE Multilin C 7 LOGICAL NODES APPENDIX C C ...
Page 476: ...E 10 B90 Low Impedance Bus Differential System GE Multilin E 1 IEC 60870 5 104 APPENDIX E E ...
Page 502: ...viii B90 Low Impedance Bus Differential System GE Multilin INDEX ...