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B30 BUS DIFFERENTIAL SYSTEM – INSTRUCTION MANUAL
FLEXLOGIC
CHAPTER 5: SETTINGS
5
only. If this rule is broken, a syntax error is declared.
5.6.3 FlexLogic evaluation
Each equation is evaluated in the ascending order in which the parameters have been entered.
5.6.4 FlexLogic example
This section provides an example of logic implementation for a typical application. The sequence of steps is important to
minimize the work to develop the relay settings. Note that the example in the following figure demonstrates the procedure,
not to solve a specific application situation.
Note that there is also a graphical interface with which to draw logic and populate FlexLogic equation entries. See the
Engineer content at the end of the previous chapter.
In the example, it is assumed that logic has already been programmed to produce virtual outputs 1 and 2, and is only a
part of the full set of equations used. When using FlexLogic, it is important to make a note of each virtual output used; a
virtual output designation (1 to 96) can be assigned only once.
Figure 5-87: Logic example
1.
Inspect the example logic diagram to determine if the required logic can be implemented with the FlexLogic
operators. If this is not possible, the logic must be altered until this condition is satisfied. Once done, count the inputs
to each gate to verify that the number of inputs does not exceed the FlexLogic limits, which is unlikely but possible. If
the number of inputs is too high, subdivide the inputs into multiple gates to produce an equivalent. For example, if 25
inputs to an AND gate are required, connect Inputs 1 through 16 to AND(16), 17 through 25 to AND(9), and the outputs
from these two gates to AND(2).
Inspect each operator between the initial operands and final virtual outputs to determine if the output from the
operator is used as an input to more than one following operator. If so, the operator output must be assigned as a
virtual output.
FlexLogic provides built-in latches that by definition have a memory action, remaining in the set state after the set
input has been asserted. These built-in latches are reset dominant, meaning that if logical "1" is applied to both set
and reset entries simultaneously, then the output of the latch is logical "0." However, they are volatile, meaning that
they reset upon removal of control power.
When making changes to FlexLogic entries in the settings, all FlexLogic equations are re-compiled whenever any
new FlexLogic entry value is entered, and as a result of the re-compile all latches are reset automatically.
To implement FlexLogic using a graphical user interface, see the FlexLogic Design and Monitoring using Engineer
section in the previous chapter.
Summary of Contents for b30
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