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Publication No. IPN250RTM-HRM/2
Switches and LEDs 27
NVMRO
CAUTION
If NVMRO is to be set elsewhere instead of on the IPN250RTM, ensure that the DIP switch/link is
set/left open.
3.1.2 PCIe Switch Configuration
LINK
Refer to
for the location of the P8 switch bank.
The
IPN250
includes
a
PCIe
switch,
some
basic
configuration
of
which
can
be
done
using
strapping
options.
These
strapping
options
may
be
adjusted
on
the
IPN250RTM
using
the
P8
DIP
switches.
Closing
a
switch
takes
the
corresponding
function
to
the
low
(GND)
state.
Upstream Port
Selection
The
upstream
port
is
selected
by
the
binary
value
set
on
switches
1
to
4
,
e.g.
00000
b
=
port
0
10000
b
=
port
16
Where
0
=
switch
closed
and
1
=
switch
open.
NOTE
Bit 3 of the port number cannot be set. It is always zero.
Station 1 Port
Configuration
The
station
1
port
configuration
is
selected
by
the
binary
value
set
of
switches
6
and
7,
as
follows:
00
b
=
x16
01
b
=
x4,
x4,
x4,
x4
10
b
=
x8,
x4,
x4
11
b
=
x8,
x8
Where
0
=
switch
closed
and
1
=
switch
open.
NOTE
An inverter has been included on the bit 0 signal line to invert operation to that described for this bit
in the PCIe switch data sheet.
Table 3-2 IPN250RTMA P8 Switch Assignments
P8
Switch
Function
Description
Associated
LED
1
NT_UPORT0
Sets the Non-Transparent Upstream port (bit 0) - see below
DS33
2
NT_UPORT1
Sets the Non-Transparent Upstream port (bit 1) - see below
DS32
3
NT_UPORT2
Sets the Non-Transparent Upstream port (bit 2) - see below
DS31
4
NT_UPORT4
Sets the Non-Transparent Upstream port (bit 4) - see below
DS30
5
NT_ENABLE~
Closed/linked = Non-transparent mode enabled
a
Open = Non-transparent mode disabled
DS29
6
EP_PCFG0~
Sets the port configuration for station 1 (bit 0) - see below
DS28
7
EP_PCFG1
Sets the port configuration for station 1 (bit 0) - see below
DS27
8
Unconnected
Leave open
-
a. In the default build state of the IPN250, this also enables the non-transparent PCI to PCI bridge.