GE Multilin
N60 Network Stability and Synchrophasor Measurement System
5-101
5 SETTINGS
5.4 FLEXLOGIC™
5
98: The gate preceding the output is an AND, which in this case requires two inputs. The operator for this gate is a 2-
input AND so the parameter is “AND(2)”. Note that FlexLogic™ rules require that the number of inputs to most
types of operators must be specified to identify the operands for the gate. As the 2-input AND will operate on the
two operands preceding it, these inputs must be specified, starting with the lower.
97: This lower input to the AND gate must be passed through an inverter (the NOT operator) so the next parameter is
“NOT”. The NOT operator acts upon the operand immediately preceding it, so specify the inverter input next.
96: The input to the NOT gate is to be contact input H1c. The ON state of a contact input can be programmed to be
set when the contact is either open or closed. Assume for this example the state is to be ON for a closed contact.
The operand is therefore “Cont Ip H1c On”.
95: The last step in the procedure is to specify the upper input to the AND gate, the operated state of digital element 2.
This operand is "DIG ELEM 2 OP".
Writing the parameters in numerical order can now form the equation for virtual output 3:
[95] DIG ELEM 2 OP
[96] Cont Ip H1c On
[97] NOT
[98] AND(2)
[99] = Virt Op 3
It is now possible to check that this selection of parameters will produce the required logic by converting the set of parame-
ters into a logic diagram. The result of this process is shown below, which is compared to the logic for virtual output 3 dia-
gram as a check.
Figure 5–38: FLEXLOGIC™ EQUATION FOR VIRTUAL OUTPUT 3
6.
Repeating the process described for virtual output 3, select the FlexLogic™ parameters for Virtual Output 4.
99: The final output of the equation is virtual output 4 which is parameter “= Virt Op 4".
98: The operator preceding the output is timer 2, which is operand “TIMER 2". Note that the settings required for the
timer are established in the timer programming section.
97: The operator preceding timer 2 is OR #2, a 3-input OR, which is parameter “OR(3)”.
96: The lowest input to OR #2 is operand “Cont Ip H1c On”.
95: The center input to OR #2 is operand “TIMER 1".
94: The input to timer 1 is operand “Virt Op 3 On".
93: The upper input to OR #2 is operand “LATCH (S,R)”.
92: There are two inputs to a latch, and the input immediately preceding the latch reset is OR #1, a 4-input OR, which
is parameter “OR(4)”.
91: The lowest input to OR #1 is operand “Virt Op 3 On".
90: The input just above the lowest input to OR #1 is operand “XOR(2)”.
89: The lower input to the XOR is operand “DIG ELEM 1 PKP”.
88: The upper input to the XOR is operand “Virt Ip 1 On".
87: The input just below the upper input to OR #1 is operand “Virt Op 2 On".
86: The upper input to OR #1 is operand “Virt Op 1 On".
85: The last parameter is used to set the latch, and is operand “Virt Op 4 On".
FLEXLOGIC ENTRY n:
NOT
FLEXLOGIC ENTRY n:
AND (2)
FLEXLOGIC ENTRY n:
=Virt Op 3
97
98
99
FLEXLOGIC ENTRY n:
DIG ELEM 2 OP
FLEXLOGIC ENTRY n:
Cont Ip H1c On
95
96
AND
VIRTUAL
OUTPUT 3
827030A2.VSD
