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(samples per cycle)

(fundamental frequency)/2

At 24 samples per cycle, this would be nominally 600 Hz for a 50 Hz system, or 720 Hz for a 60 Hz system.

The following figure shows the nominal frequency response of the anti-alias filter and the Fourier filter for a 24-
sample single cycle fourier algorithm acting on the fundamental component:

Ideal anti-alias filter response

Real anti-alias filter

response

2 3 4

0.2

0.4

0.6

0.8

5 6 7 8 9 10 11 12 13

14 15 16 17 18 19 20 21 22 23 24

50 Hz

600 Hz

1200 Hz

V00301

Fourier response without

anti-alias filter

Fourier response with

anti-alias filter

Alias frequency

Figure 14: Frequency Response (indicative only)

5.4

PROGRAMMABLE SCHEME LOGIC

The purpose of the programmable scheme logic (PSL) is to allow you to configure your own protection schemes to
suit your particular application. This is done with programmable logic gates and delay timers. To allow greater
flexibility, different PSL is allowed for each of the four setting groups.

The input to the PSL is any combination of the status of the digital input signals from the opto-isolators on the
input board, the outputs of the protection elements such as protection starts and trips, and the outputs of the fixed
protection scheme logic (FSL). The fixed scheme logic provides the standard protection schemes. The PSL consists
of software logic gates and timers. The logic gates can be programmed to perform a range of different logic
functions and can accept any number of inputs. The timers are used either to create a programmable delay,
and/or to condition the logic outputs, such as to create a pulse of fixed duration on the output regardless of the
length of the pulse on the input. The outputs of the PSL are the LEDs on the front panel of the relay and the output
contacts at the rear.

The execution of the PSL logic is event driven. The logic is processed whenever any of its inputs change, for
example as a result of a change in one of the digital input signals or a trip output from a protection element. Also,
only the part of the PSL logic that is affected by the particular input change that has occurred is processed. This
reduces the amount of processing time that is used by the PSL. The protection & control software updates the logic
delay timers and checks for a change in the PSL input signals every time it runs.

The PSL can be configured to create very complex schemes. Because of this PSL desing is achieved by means of a
PC support package called the PSL Editor. This is available as part of the settings application software MiCOm S1
Agile, or as a standalone software module.

5.5

EVENT RECORDING

A change in any digital input signal or protection element output signal is used to indicate that an event has taken
place. When this happens, the protection and control task sends a message to the supervisor task to indicate that
an event is available to be processed and writes the event data to a fast buffer controlled by the supervisor task.
When the supervisor task receives an event record, it instructs the platform software to create the appropriate log
in non-volatile memory (flash memory). The operation of the record logging to SRAM is slower than the supervisor
buffer. This means that the protection software is not delayed waiting for the records to be logged by the platform
software. However, in the rare case when a large number of records to be logged are created in a short period of
time, it is possible that some will be lost, if the supervisor buffer is full before the platform software is able to create
a new log in SRAM. If this occurs then an event is logged to indicate this loss of information.

GE P24DM, Technical Manual

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