Publication No. SBC330-0HH/3
Functional Description 41
5.8 Timers
There
are
a
range
of
timers
available
on
the
SBC330.
5.8.1 Internal processor timers
The
8641D
provides
eight
31
‐
bit
general
‐
purpose
timers.
Each
timer
can
generate
interrupts
to
either
or
both
processing
cores
and
can
be
programmed
to
generate
periodic
interrupts.
Each
group
of
4
timers
can
be
set
to
operate
from
a
divider
of
the
MPX
bus
clock
(divided
by
8,
16,
32,
or
64)
or
from
an
external
14.318
MHz
clock.
The
minimum
resolution
of
each
timer
is
15
ns.
Each
group
of
timers
can
be
cascaded
to
form
two
63
‐
bit
timers,
one
95
‐
bit
timer
or
one
127
‐
bit
timer,
if
required.
5.8.2 Watchdog timers
The
SBC330
provides
two
independent,
programmable
16
‐
bit
watchdog
timers,
each
one
can
be
driven
from
a
‘fast’
or
‘slow’
clock.
These
are
count
‐
down
timers,
which
are
capable
of
generating
interrupts
to
either
or
both
of
the
two
processing
cores
at
a
programmable
threshold
and
resetting
the
board
if
expired.
The
watchdog
timers
are
disabled
following
reset,
but
once
enabled,
the
watchdog
must
be
serviced
periodically
to
prevent
a
reset.
Further
details
on
the
operation
of
the
watchdogs
can
be
found
in
the
Watchdog
Registers
section.
5.9 AXIS Support
The
SBC330
provides
hardware
features
required
to
support
GEIP’s
AXIS
software
suite.
Four
32
‐
bit
wide
FIFOs,
capable
of
holding
64
messages
each,
are
provided
to
support
message
passing
between
the
two
on
‐
board
processing
nodes
or
from
other
nodes
in
the
system
to
the
on
‐
board
processing
nodes.
An
interrupt
can
be
generated
to
the
receiving
processing
node
when
a
message
is
received,
and
remains
asserted
until
the
message
queue
is
empty.
The
SBC330
supports
a
48
‐
bit
timer,
clocked
by
the
external
AXIS_TIMER_CLK
signal
and
reset
by
the
AXIS_TIMER_RST
signal.
The
SBC330
can
Master
(drive)
these
signals
or
receive
them.
This
allows
several
boards
to
be
connected
to
these
signals
and
generates
a
common
timestamp
for
data
passed
between
them.
Hardware
semaphores
are
also
provided
for
use
in
locking
common
resources.
NOTE
The AXIS Timer Clock and Reset signals are shared with GPIO0 and GPIO1 respectively, and there is
no hardware separation of the two functions. When using AXIS functionality, ensure that GPIO0 and
GPIO1 are set to Input mode, and interrupt generation is disabled (the default state). Likewise, when
AXIS functionality is not being used, ensure that the AXIS interrupts are masked (the default state).
