Publication No. SBC330-0HH/3
FPGA Registers 51
6.3 Board Revision Register
This
records
the
revision
of
the
board,
the
FPGA
and
the
CPLD
release.
This
is
useful
in
identification
and
to
system
or
FTS
software,
which
may
need
to
change
behavior
according
to
any
of
these
parameters.
At
present,
PCB
revisions
are
recorded,
although
minor
changes
in
FPGA
or
CPLD
code
may
not
be
recorded.
The
register
is
read
‐
only,
hard
‐
coded
and
cannot
be
updated
by
any
software.
The
register
is
echoed
in
power
up
defaults
loaded
into
the
M8641
on
the
Local
AD
bus
lines.
This
replication
is
for
ease
of
use
with
an
emulator.
Chip
Select
CS2
Offset
0x000C
Reset
value
Depends
on
board
revision
LAD Bit
Reg Bit
R/W
Description
15
0
R
PCB rev bit 0
14
1
R
PCB rev bit 1
13
2
R
PCB rev bit 2
12
3
R
PCB minor rev bit 0
11
4
R
PCB minor rev bit 1
10
5
R
FPGA rev bit 0
9
6
R
FPGA rev bit 1
8
7
R
FPGA rev bit 2
7
8
R
FPGA rev bit 3
6
9
R
FPGA rev bit 4
5
10
R
CPLD rev bit 0
4
11
R
CPLD rev bit 1
3
12
R
CPLD rev bit 2
2
13
R
Power Manager rev bit 0
1
14
R
Power Manager rev bit 1
0
15
R
Power Manager rev bit 2
