38 VMIVME-7807/VME-7807RC Hardware Reference Manual
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3.3.10 Timer 2 IRQ Clear (T2IC)
The
Timer
2
IRQ
Clear
(T2IC)
register
is
used
to
clear
an
interrupt
caused
by
Timer
2.
Writing
to
this
register,
located
at
offset
0x34
from
the
address
in
BAR2,
causes
the
interrupt
from
Timer
2
to
be
cleared.
This
can
also
be
done
by
writing
a
“0”
to
the
appropriate
“Timer
x
Caused
IRQ”
field
of
the
timer
Control
Status
Register
(CSR1).
This
register
is
write
only
and
the
data
written
is
irrelevant.
3.3.11 Timer 3 IRQ Clear (T3IC)
The
Timer
3
IRQ
Clear
(T3IC)
register
is
used
to
clear
an
interrupt
caused
by
Timer
3.
Writing
to
this
register,
located
at
offset
0x38
from
the
address
in
BAR2,
causes
the
interrupt
from
Timer
3
to
be
cleared.
This
can
also
be
done
by
writing
a
“0”
to
the
appropriate
“Timer
x
Caused
IRQ”
field
of
the
timer
Control
Status
Register
(CSR1).
This
register
is
write
only
and
the
data
written
is
irrelevant.
3.3.12 Timer 4 IRQ Clear (T4IC)
The
Timer
4
IRQ
Clear
(T4IC)
register
is
used
to
clear
an
interrupt
caused
by
Timer
4.
Writing
to
this
register,
located
at
offset
0x3C
from
the
address
in
BAR2,
causes
the
interrupt
from
Timer
4
to
be
cleared.
This
can
also
be
done
by
writing
a
“0”
to
the
appropriate
“Timer
x
Caused
IRQ”
field
of
the
timer
Control
Status
Register
(CSR1).
This
register
is
write
only
and
the
data
written
is
irrelevant.