The modulating input signal (internal or external in origin) is received by switch U3B (jumpers
P2 and P3 control the input impedance for the external modulation input; normally it is 50
ohms). Between U3B and a second switch (U3A) are two paths for the modulating signal: An
AM path includes scaling and logarithmic amplification circuits (U2B, U1, U4, U2A) needed in
the Linear AM mode, and a Scan path which bypasses these. After U3A, the modulating signal
passes through a shaper circuit (U5) which compresses its range to
±
1 V so that it can drive
U12, an analog-to-digital converter.
The digital outputs of the ADC are applied to the address switches (U19, U20, U21) to control
addressing of the RAMs U22, U23, and U24. Together, these RAMs make up a 4K x 12 volatile
memory (scan module correction data are downloaded into this memory from ROM when scan
modulation is selected).
As the modulating input changes, the digital output of the ADC tracks it, retrieving from RAM
the appropriate correction data at each point. The data from RAM is applied to the U29 DAC,
which converts it into an analog control signal to drive the scan module (via U44 and U45).
For internal modulation, the U39 DAC is used by the computer to add an offset to the internal
modulating signal to control the depth of modulation. The DAC output, amplified by U40A and
U40B, is summed with the internal modulating signal at U38-6. Switch U37B controls the gain
of U40B, which is reduced by half when the variable attenuation mode is selected.
3.3.10
Level — PC Assembly A10
The leveling scheme used in the GT 9000 series can be compared to a Phase Locked Loop. The
similarities are that the leveling loop has a reference and a variable input which are compared,
and the loop action adjusts the variable input (proportional to the actual unit output level) until
the two inputs are balanced. The comparison is made at the summing junction of an op amp
integrator. The output of the integrator controls PIN leveling diodes to adjust the RF power
level. The power level is detected and amplified as required, and returned as the variable input
to the integrator.
On this board U17A is the op-amp integrator. Its summing junction at pin 2 compares a
reference input and the detected RF input. The reference input is the REFX20 input from the
detector buffer module A200, which is amplified by U15. The gain is adjustable via pots R27
(GAIN
∞
2 for downconverter frequencies) and R29 (GAIN >2 for frequencies >2GHz) and is
switched by U14A and B, depending on the output frequency. The variable input to the U17
summing junction is the actual RF detector voltage, which has been amplified at the detector
buffer module A200. Q2 samples this signal (DETX20) when the unit is pulse modulated. When
the unit is not pulse modulated, Q2 is turned on and the detector voltage, buffered by U30, can
be inverted by U27, depending on whether the detector voltage is negative or positive. This
inversion is controlled by switch U16A and B. In addition to these two inputs to the summing
junction of U17, offset voltages are summed in as well. Two different adjustable offsets (R28
and R30) are available and are switched by U14A and B depending on whether the output
frequency is > or à 2 GHz. Q1 samples the signals at this summing point when in pulse
modulation mode or, if pulse is turned off, Q1 is turned on all of the time. The summing
integrator U17A has variable feedback paths available. U18A and B are switched in as
appropriate for different leveling modes. The output of the amplifier is fed to U19 via CR1 and
CR2. This serves as a window detector to detect when the leveling loop is unleveled. When the
loop is unleveled, U19-7 goes low to light DS1 and send a low logic signal to the computer. The
output of the U17A amplifier is also amplified by U17B. Its gain is adjustable via the R50
Theory of Operation
Manual No. 120AM00250, Rev C, September 1998
3-23
Summary of Contents for GT 9000
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