3.3.13
100 MHz Reference PLL — PC Assembly A14
This circuit phase locks the 100 MHz oscillator (A201) to the internal 10 MHz timebase or to
an external timebase. In addition to the loop output, it produces a lock indicator signal and a set
of buffered 10 MHz outputs used as references for other loops in the instrument.
The 100 MHz input at J5 is buffered by U10B before being divided down to 10 MHz by U4.
The 10 MHz is then buffered by U8A, B, C and U9A, B and C so that it can be used by other
circuits in the unit which require a 10 MHz reference. The signal is also applied to the variable
input of the phase detector U5-9.
The reference input to the phase detector U5-6 comes from a switching circuit, which selects
either an internal or external 10 MHz reference. When no external reference is present at J3, the
internal 10 MHz reference at J4 (buffered by U11A) is allowed to propagate through U12C and
on to the phase detector (U5-6). When an external 10 MHz signal is present at J3, it is buffered
by U11A and allowed to propagate through U12A to the phase detector. The presence of an
external 10 MHz reference is detected when C38 is charged, causing the switching circuit
(comparator U14) to switch to a high state. This causes the U13 output to go high to turn off
the supply to the internal 10MHz reference. The switching circuit also enables the external
reference path at U12A and disables the internal reference at U12C. The selected reference is
then available through Q1 and Q2 as the 10 MHz reference output on the rear panel.
The phase comparator U5 compares the 10 MHz reference with the output of the divider U4 and
determines which signal leads or lags the other. The output pulses at U5-12 and U5-3 are
integrated or filtered by U6B, resulting in a tuning or correction voltage at J6 which will steer
the 100 MHz VCXO oscillator in the proper direction (a more positive voltage increases
frequency) to acquire and sustain a locked condition. When the loop is phase locked (the
reference and variable input frequency and phase are equal), the output pulses of the phase
detector will be extremely narrow at a 10 MHz rate. U7, CR1 and CR2 along with other
components serve as a window detector which detects the tuning voltage and unlocked
conditions. When the loop unlocks, U7-7 goes low, lighting DS1 and sending the unlock logic
level to the computer via U2, a tri-state buffer which serves as the interface to the bus. U1 is a
3-to-8 decoder for decoding chip selects.
U3 reg22 V to +15 V, which is then filtered by L1, C16 and C17 to provide a clean
voltage for U6, thereby reducing noise introduced by the tuning voltage to the oscillator.
Model GT 9000 Microwave Synthesizer
3-26
Manual No. 120AM00250, Rev C, September 1998
Summary of Contents for GT 9000
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