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3.3.15

Reference / Downconverter PLL — PC Assembly A16

Reference PLL

The Reference Phase Locked Loop circuit contains the Reference PLL, and the Downconverter
(or Fixed LO) PLL circuitry as well as the logic and drivers for the Downconverter filters. The
Reference PLL fine tunes the reference YIG oscillator to phase lock it to a harmonic of the
100 MHz oscillator (see A201) and ultimately to the instrument timebase. The U5 phase
detector compares two 5 MHz inputs, one from the reference sampler IF (J2), buffered by U1C,
and the other one from the internal or external input (J4 or J3 respectively). If the two 5 MHz
inputs are out of phase, wide pulses will appear at one of U5 outputs (pins 3 or 12, depending
on which input is leading). The filter/amplifiers (U6A and B and associated components)
convert these pulses into a correction voltage which is filtered by L1, C12 and C13 and then
supplied to U9, which drives the fine tuning (or FM) coil of the reference YIG oscillator. The
PLL circuit adjusts the frequency of the oscillator in whichever direction will reduce the phase
difference between the two 5 MHz inputs. The PLL output goes more positive to increase
frequency and more negative to decrease it.

The reference frequency is mixed with a 100 MHz comb line and should be 5 MHz above the
100 MHz multiple. If the reference frequency falls above the desired multiple, the output
voltage at U6-1 will be higher than normal. The kicker circuit U7A and associated components
will detect this by comparing the voltage with a reference voltage set by R30, R31 and kick the
output of U6B high, resulting in the output of U6A going low, decreasing the oscillator
frequency. If the output frequency is too low, the kicker circuit U7B and associated components
will detect the output of U6A being below a certain voltage level (set by R79, 32 and 33) and
kick U6 such that the output at pin 1 will go high, thereby increasing the output frequency.
Whenever the circuits (U7) kick, C10 or C9 are charged so that the lock detector U8 pulls the
REF_LOCK signal low, thereby illuminating the lock LED DS1.

The 5 MHz input to the phase detector is derived either from the 10 MHz input at J4 or from
the 5-6 MHz input at J3. The 5-6 MHz input, if present must be detected so that the 10 MHz
path will be disabled. This is achieved by delaying one input to U2B with R7 and C3. This
causes U2-3 output to be low and disable the 10 MHz from propagating thru U3A. Instead, the
5-6 MHz input propagates thru to the phase detector U5. When no 5-6 MHz input is present, the
10 MHz propagates thru U3A and B, being divided by two, and then thru U2C to the phase
detector input.

At some output frequencies the sampler IF is 1.667 MHz rather than 5 MHz. In this situation,
the control input at Q1 enables flip-flop U4 to remove two pulses out of every three coming
from either U2-2 or U3-15. This effectively divides the 5 MHz by three, which yields the
desired 1.667 MHz signal.

Downconverter PLL

The Downconverter PLL (or Fixed LO PLL) circuitry is similar to the Reference PLL. One
difference is that there is only one set of inputs to the phase detector U11, the 10 MHz and the
DC sampler IF. When the loop is locked, the DC sampler IF should be 5 MHz, the flip flop U12
divides the 10 MHz reference by two yielding 5 MHz. The other difference is that this loop is
turned off by U16 and Q2 when the unit is not operating in the downconverter range. This
reduces spurs and noise which can be added by this circuitry when it is not locked.

This board also provides downconverter filter drive logic. U17 is a 4-to-16 decoder which
decodes logic from the computer to select each of the downconverter filters as appropriate via

Giga-tronics GT 9000, Operation & Maintenance Manual

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