BIOS Setup
- 105 -
Parameter
Description
Target Static Lane Select
Upper 32 bits
This item is configurable when
Target Static Lane Control
is set to
Enabled
.
Target Static Lane Select
Lower 32 bits
This item is configurable when
Target Static Lane Control
is set to
Enabled
.
Target Static Lane Select
ECC
This item is configurable when
Target Static Lane Control
is set to
Enabled
.
Target Static Lane Value
This item is configurable when
Target Static Lane Control
is set to
Enabled
.
Worst Case Margin
Granularity
Configures Worst Case Margin Granularity.
Options available: Per Chip Select, Per Nibble.
Default setting is
Per Chip Select.
Read Voltage Sweep Step
Size
Configures the step size for read Data Eye voltage sweep.
Options available: 1, 2, 4. Default setting is
1
.
Read Timing Sweep Step
Size
Configures the step size for read Data Eye timing sweep.
Options available: 1, 2, 4. Default setting is
1
.
Write Voltage Sweep Step
Size
Configures the step size for write Data Eye voltage sweep.
Options available: 1, 2, 4. Default setting is
1
.
Write Timing Sweep Step
Size
Configures the step size for write Data Eye timing sweep.
Options available: 1, 2, 4. Default setting is
1
.
Summary of Contents for G492-ZL2
Page 1: ...G492 ZL2 HPC Server 4U DP SXM4 A100 8 GPU Server User Manual Rev 1 0 ...
Page 51: ...BIOS Setup 51 When Boot Mode Select is set to Legacy in the Boot Boot Mode Select section ...
Page 63: ...BIOS Setup 63 5 2 8 PCI Subsystem Settings ...
Page 74: ... 74 BIOS Setup 5 2 17 Intel R X710 Ethernet Controller ...