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1

Introduction

The Glitch Works R6501Q/R6511Q (GW-R65X1QSBC-1) is a single-board computer (SBC) com-
patible with Rockwell’s R6501Q and R6511Q one-chip microprocessors (referred to as the R65X1Q)
in plastic QUIP (Quad Inline Package). The SBC is also compatible with the high speed A suffix
Rockwell parts. It includes the following features:

Rockwell R6501Q, R6511Q, R6501AQ, or R6511AQ

32 KB static RAM, FeRAM compatible

32 KB ROM, EEPROM, or FeRAM in 4K pages, in-board programmable

Serial console via onboard UART

ROM paging and switch-out

Debounced reset and power supply supervisory circuit

Glitchbus expansion header

Glitchbus I/O mapped as a 256 byte memory page at

0xEF00

The R65X1Q SBC includes a modified version of the eWoz monitor with customization for the
R65X1Q onboard UART and memory layout. With the addition of a serial terminal (or terminal
emulation software on a PC), the SBC provides a basic self-contained R65X1Q system. The SBC’s
ROM implementation is compatible with Glitch Works ROMFS, which allows for the storage of file
records in ROM. These records can be loaded from the monitor, or automatically selected by option
switches on reset/power-up. This also allows for in-board updates without overwriting the current,
known-good copy of a program.

Two of the onboard R65X1Q parallel I/O ports are brought out to 5x2 pin headers on 0.1” centers.
These ports are unused by the standard ROM software load and are available for user applications.
See the R6500 applications manual specific to the processor used for more information.

2

Configuration

The R65X1Q SBC includes a switch pack and several optional resistors for configuring system op-
tions:

Name

Function

SW2

ROM write protect, ROMFS program select, bitrate selection

R1-R3, R6

Installed only for R6511Q/R6511AQ processors

For normal operation with standard ROM images, SW2 should have all switches set to the

OFF

position.

Console bitrate is selected with SW2 positions 3 and 4. The default configuration, with SW2 positions
3 and 4 off will provide a 4800 bps console with a 1 MHz system clock, or a 9600 bps console with a
2 MHz system clock.

Review notes in the following section concerning the selection of bitrates and

potential error in higher speed rates

.

2

Summary of Contents for GW-R65X1QSBC-1

Page 1: ...11Q SBC GW R65X1QSBC 1 User s Manual and Assembly Guide Revision 2 2020 10 03 c 2020 Glitch Works LLC http www glitchwrks com This manual is licensed under a Creative Commons Attribution NonCommercial...

Page 2: ...6 3 3 Insert Socketed ICs 6 3 4 Assemble Console Cable 7 3 5 Optional Glitchbus Expansion 7 4 Initial Checkout and Testing 8 4 1 Troubleshooting 8 4 2 Repair and Service 8 5 Technical Notes 9 5 1 Por...

Page 3: ...r the storage of file records in ROM These records can be loaded from the monitor or automatically selected by option switches on reset power up This also allows for in board updates without overwriti...

Page 4: ...speed is required it is recommended that a 2 MHz system clock be used While Rockwell only specs the A suffix R6501AQ and R6511AQ for 2 MHz operation internal testing has shown good results with runni...

Page 5: ...e or below the SBC using PC 104 style stacking headers The R65X1Q SBC can also be used with right angle headers and a Glitchbus backplane The Glitchbus includes signals for separate memory and I O add...

Page 6: ...com adafruit guide excellent soldering 3 1 Assembling the R65X1Q SBC If you purchased a full Glitch Works parts kit we recommend completing all assembly sections since extra features can be disabled a...

Page 7: ...essors due to the force required for insertion and removal Note that QUIP package processors have a big notch at both ends and a smaller off center notch to indicate pin 1 Install 33 F 35 V capacitor...

Page 8: ...ins for software control Consult the schematic for more information A serial light box will help debug potential serial wiring problems we highly recommend the addition of a light box to your toolkit...

Page 9: ...ng If your R65X1Q SBC fails to come up recheck all solder joints for cold joints bridges or missed pins this is by far the most common problem we ve observed during assembly workshops Recheck con figu...

Page 10: ...lable at 0xF000 These bits are set on reset so that the last page of ROM is available for booting Writing to these bits immediately changes the ROM page Port C provides readback of these bits Bit 3 en...

Page 11: ...Glitch Works software to select the ROMFS record to load into memory at reset PA4 PA5 are used by Glitch Works software to set the console UART bitrate as described in Section 2 1 Configuring Console...

Page 12: ...1 ROM Compatibility The ROM socket at U2 is compatible with JEDEC standard 32K x 8 static RAM Ferroelectric RAM FeRAM and 28C256 EEPROMs It may not be compatible with some manufacturers UV EPROMs such...

Page 13: ...ve 1x 4 MHz crystal 1x Rockwell R6501Q CPU 1x 28C256 EEPROM preloaded with R65X1Q SBC firmware 1x JEDEC 62256 type 32K x 8 static RAM 1x 74LS04 hex inverter 1x 74LS10 triple 3 input NAND gate 1x 74LS2...

Page 14: ...parts list may be shipped as a 7404 74S04 74F04 74LS04 74ALS04 or 74HCT04 All 4 7 k resistors on the GW R65X1QSBC 1 are pull up or pull down resistors and may be any value from 2 2 k to 10 k even thou...

Page 15: ......

Page 16: ...CE 20 A10 21 OE 22 A11 23 A9 24 A8 25 A13 26 WE 27 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 U2 32K ROM A7 A6 A5 A4 A3 A2 A1 A0 RPA0 A11 A10 A9 A8 RPA2 RPA1 D0 D2 D4 D6 D1 D3 D5 D7 C11 22p C10 22p GND GND 1...

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