5
Technical Notes
5.1
Port C and Board Control Register
The R65X1Q SBC uses a portion of the onboard Port C parallel I/O port (
0x0002
) as a board control
register. Certain bits of Port C are used internally for “Full Address Mode,” while others are used
to control ROM operation. Port C is addressed at memory location
0x0002
. The bits of Port C are
mapped as follows:
Port C Bit
Function
Notes
0
ROM Page Address, bit 0
Set on reset
1
ROM Page Address, bit 1
Set on reset
2
ROM Page Address, bit 2
Set on reset
3
ROM Disabled
Set (ROM enabled) on reset
4
Unused
5
Unused
6
Address Bus
A13
Not user controllable
7
Address Bus
A14
Not user controllable
Bits 0 through 2 control the selected 4K page of ROM available at
0xF000
. These bits are set on reset
so that the last page of ROM is available for booting. Writing to these bits immediately changes the
ROM page. Port C provides readback of these bits.
Bit 3 enables ROM when set, and disables ROM when clear. This allows unmapping ROM for use
of system memory at
0xF000
. Writing a 0 to this bit clears it and immediately switches off ROM,
writing a 1 to this bit switches ROM in. The selected ROM page is not affected. Bit 3 is set (ROM
enabled) on reset. Its status can be read back through Port C.
Bits 4 and 5 are unused and can be jumpered to end user applications, if desired.
Bits 6 and 7 control address bus lines
A13
and
A14
, respectively. These bits are used in the “Full
Address Mode” configuration of the R65X1Q processor, and are not available for user control as I/O
pins. See the R6500 family datasheet relevant to the chosen processor for more information.
9
Summary of Contents for GW-R65X1QSBC-1
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