PCI Master Read Caching
To enable this function, the CPU L2 cache will be used to cache PCI master
reads. This boosts the performance of PCI master. It's recommend to disable
this feature
PCI Master Broke n Tim er
To enable this feature allows for slower PCI bus mastering expansion cards.
PCI # 2 Access # 1 Retry
This BIOS feature is linked to the CPU to PCI Write Buffer. Normally, the CPU to
PCI Write Buffer is enabled. All writes to the PCI bus are, as such, immediately
written into the buffer, instead of the PCI bus. This frees up the CPU from
waiting till the PCI bus is free. The data are then written to the PCI bus when
the next PCI bus cycle starts.
There's a possibility that the buffer write to the PCI bus may fail. When that
happens, this BIOS option determines if the buffer write should be reattempted
or sent back for arbitration. If this BIOS option is enabled, then the buffer will
attempt to write to the PCI bus until successful. If disabled, the buffer will
flush its contents and register the transaction as failed. The CPU will have to
write again to the write buffer. It is recommended that you enable this feature
unless you have many slow PCI devices in your system. In that case, disabling
this feature will prevent the generation of too many retries which may severely
tax the PCI bus.
ISA Bus Clock
Allows you to set the speed of the ISA bus in fractions fo the PCI bus speed,
so if the PCI bus is operating at its theroretical maximum, 33Mhz, PCICLK/3
would yield an ISA speed of 11Mhz. The choices: 7.159Mhz, PCICLK/4 and
PCICLK/3.
AGP Master 1 WS Write
By default, the AGP busmastering device waits for at least 2 wait states or
AGP clock cycles before it starts a write transaction. This BIOS option allows
you to reduce the delay to only 1 wait state or clock cycle. For better AGP
write performance, enable this option but disable it if you experience weird
graphical anomalies like wireframe effects and pixel artifacts after enabling
this option.
AGP Master 1 WS Read
By default, the AGP busmastering device waits for at least 2 wait states or
AGP clock cycles before it starts a read transaction. This BIOS option allows
you to reduce the delay to only 1 wait state or clock cycle. For better AGP
read performance, enable this option but disable it if you experience weird
graphical anomalies like wireframe effects and pixel artifacts after enabling
this option.
3312400 User's Manual
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