Users Manual
Model 3600
www.globalspecialties.com
Page 19
desired signals and saves memory space.
Sampling Cycle
The logic analyzer captures data on the hop edge of the sampling clock
and the data between two hop edges is ignored. (hop edge means the
moment of potential shifting). If a longer sampling cycle is chosen,
the fast-changing sections of the input signals will be missed. This
causes the displayed waveforms to have distortion compared to the
true waveforms of the input signals both in amplitude and time. One
should use a shorter sampling cycle in order to observe the particular
changes of the tested signals, that is, to increase the sampling rate. It
is recommended the sampling cycle should be 3-5 times less than the
narrowest pulse width of the tested signals. In other words, even the
narrowest pulse of the tested signals should include three sampling
points at least, which can truly reflect input signals’ change as time.
The instrument uses an internal clock in the time sampling and the
clock cycle can be set. Press
【
system
】
to select parameter pattern-
clk and input the clock cycle value with decimalization numbers 0~9.
Its unit is ns, resolution is 10ns, the last number on the right is to
be ignored as it has no use. The minimum cycle value is 10 ns; the
maximum value is 999999990ns, approximate to 1s. When the code
generator’s clock is changed, the waveform’s display change is visible.
The default setting of the clock cycle is 10 ns, meaning the highest
sampling velocity is 100 MHz.
The instrument uses the external clock cycle in state sampling; the
sampling cycle can’t be changed optionally. One needs to select the
suitable signals as the sampling clock according to the state of the
tested signals.
Sampling Phase
The logic analyzer uses the sampling clock’s rising edge for obtaining
data. However the user should choose the clock’s function edge
according to the logical relation between the signal and system clock
of tested system. For instance, if various logic levels change within the
system clock’s rising edge and samples use the rising edge the timing is
not consistent, then various logic levels are changing and the sampled
data may be wrong. By choosing the falling edge in this situation,
all logic levels are in a stable state and sampled data will be correct.
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7/2/2010 4:41:46 PM
