3 Technical Description
G PCIe 6281
11
3.4.1 Block Diagram
Figure 3.2 Block Diagram of the
G PCIe 6281
Multibus Controller
3.4.2 Pin Assignment
For connecting the communication interfaces a total of four
RJ.5
connectors are provided. On each of the RJ.5
connectors are the signals from two bus interfaces and one digital IN and one digital OUT signal.
Pin
RJ.5 - Nr.1
RJ.5 - Nr.2
RJ.5 - Nr.3
RJ.5 - Nr.4
1
TRX1-DATA P
TRX3-DATA P
TRX5-DATA P
TRX7-DATA P
2
TRX1-DATA N
TRX3-DATA N
TRX5-DATA N
TRX7-DATA N
3
TRX2-DATA P
TRX4-DATA P
TRX6-DATA P
TRX8-DATA P
4
TRX2-DATA N
TRX4-DATA N
TRX6-DATA N
TRX8-DATA N
5
EXT V
BAT
1
EXT V
BAT
2
EXT V
BAT
3
EXT V
BAT
4
6
GND_ISO
GND_ISO
GND_ISO
GND_ISO
7
Digital IN1
Digital IN2
Digital IN3
Digital IN4
8
Digital OUT1
Digital OUT2
Digital OUT3
Digital OUT4
Shield
GND
GND
GND
GND
Table 3.4 Pin assignment of the RJ.5 connector
Figure 3.3 Numbering of the RJ.5 connectors
