GR551x Overview
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256 KB RAM with retention (four 8 KB RAM blocks and seven 32 KB RAM blocks) for GR5515 series SoCs,
and 128 KB RAM with retention (four 8 KB RAM blocks and three 32 KB RAM blocks) for the GR5513 SoC.
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1 MB Flash for GR5515 series SoCs (The GR5515I0ND SoC uses external QSPI Flash with various model
options.) and 512 KB Flash for the GR5513 SoC.
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Power management
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On-chip DC-DC Converter
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On-chip I/O LDO to provide I/O voltage and supply external components
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Supply voltage: 1.7 V to 3.8 V (The supply voltage of the GR5515I0ND SoC is equal to the working voltage of
external SPI Flash.)
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I/O voltage: 1.8 V to 3.3 V (Typical) (On GR5515I0ND, VDDIO0 is bonded to VIO_LDO_OUT internally and
I/O LDO is set to off mode in the application firmware by default, so VIO_LDO_OUT shall be connected to
VBATL.)
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OFF mode: 0.15 µA (Typical); nothing is on except VBAT, chip in reset mode
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Ultra deep sleep mode: 0.65 µA (Typical); I/O LDO off, no memory retention. Wake-up on an external GPIO
or an internal Timer.
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Sleep mode: 1.3 µA (Typical); Bluetooth LE link alive, I/O LDO off, supporting AON_RTC, AON GPIO and
Bluetooth LE Event, memory retention and wake-up on an external GPIO or an internal Timer.
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Peripherals
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2 x QSPI interfaces, up to 32 MHz
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2 x SPI interfaces (1 SPI Master Interface with 2 slave CS pins + 1 SPI Slave Interface), up to 32 MHz
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2 x I2C interfaces at 100 kHz, 400 kHz, 1 MHz, 2 MHz
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2 x I2S interfaces (1 I2S Master Int 1 I2S Slave Interface)
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2 x UART interfaces, one with DMA channel.
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13-bit ADC, up to 1 Msps, 8 channels (5 external test channels and 3 internal signal channels), supporting
both single-ended and differential inputs
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ISO 7816 interface
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6-channel PWM
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Built-in temperature and voltage sensors
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4 x Hardware timers
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1 x AON hardware timer
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2 x Watchdog timers(1 System Watchdog Timer and 1 Always-on watchdog timer)
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Calendar timer
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Wake-up comparator
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