GOWIN USB 2.0 SoftPHY IP User Manual Download

Page: 13 / 19

3 Functional Description

3.2 USB 2.0 SoftPHY External Circuit Connection

IPUG781-1.5.1E

7(12)

3.2

USB 2.0 SoftPHY External Circuit Connection

USB 2.0 SoftPHY supports high speed mode (480Mbps) . When the

USB 2.0 SoftPHY is used as a USB slave device, the external circuit
connection is as follows.

Figure 3-2 USB Slave Device Interface Implementation

Data+

Data-

Gowi n

FPGA

USB Device

USB 2.0 SoftPHY

usb_dxp_io

usb_pullup_en_o

usb_term_dp_o

usb_term_dn_o

90ohm

trace matching

As close to FPGA

as possible

usb_rxdn_i

usb_rxdp_i

VCC3P3

R7 C1

R1:1.5K ohm
R2:0 ohm
R3:0 ohm
R4:42 ohm
R5:42 ohm
R6:1.8K ohm
R7: 75 ohm(1N Series)

，

56 ohm(2A Series)

C1:1uF

R2 R3

Note!

1. You can see the followings for the IO port attribute constraints of GW2A series of

FPGA.



usb_dxp_io: IO_TYPE= LVCMOS33D PULL_MODE= NONE DRIVE=4;



usb_term_dn_o: IO_TYPE=LVCMOS33 PULL_MODE= NONE DRIVE=8;



usb_term_dp_o: IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8;



usb_pullup_en_o: IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8;



usb_rxdn_i: IO_TYPE=LVDS25 PULL_MODE=NONE;



usb_rxdp_i: IO_TYPE=LVDS25 PULL_MODE=NONE.

Summary of Contents for USB 2.0 SoftPHY IP

Page 1: ...Gowin USB 2 0 SoftPHY IP User Guide IPUG781 1 5 1E 07 20 2022 ...

Page 2: ... any denotes electronic mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEM...

Page 3: ... Chapter 2 3 Using 5V Host Supply to Power USB Device Solution added 12 23 2021 1 3E The configuration method of peripheral circuit modified IO configuration constraints added 03 29 2022 1 4E The description of resource utilization added 06 20 2022 1 5E The speed grade modified The description of pin constraints updated 07 20 2022 1 5 1E A note added in Table 2 1 ...

Page 4: ...rminology and Abbreviations 1 1 4 Support and Feedback 2 2 Introduction 3 2 1 Overview 3 2 2 Features 3 2 3 Using 5V Host Supply to Power USB Device Solution 4 2 4 Resource Utilization 5 3 Functional Description 6 3 1 USB 2 0 SoftPHY Block Diagram 6 3 2 USB 2 0 SoftPHY External Circuit Connection 7 4 Signal Description 9 5 Interface Configuration 11 ...

Page 5: ...ure 3 1 USB 2 0 SoftPHY Block Diagram 6 Figure 3 2 USB Slave Device Interface Implementation 7 Figure 3 3 GW1NSR 4 Pinout 8 Figure 5 1 IP Core Generator 11 Figure 5 2 Open USB 2 0 SoftPHY IP Core 12 Figure 5 3 USB 2 0 SoftPHY IP Configuration Interface 12 ...

Page 6: ...of Tables Table 1 1 Terminology and Abbreviations 2 Table 2 1 Gowin USB 2 0 SoftPHY IP Overview 3 Table 2 2 DC Electrical Characteristics 4 Table 2 3 Resource Utilization І 5 Table 2 4 Resource Utilization Ⅱ 5 Table 4 1 Signal Description 9 ...

Page 7: ...www gowinsemi com DS100 GW1N series of FPGA Products Data Sheet DS117 GW1NR series of FPGA Products Data Sheet DS821 GW1NS series of FPGA Products Data Sheet DS871 GW1NSE series of FPGA Products Data Sheet DS861 GW1NSR series of FPGA Products Data Sheet DS891 GW1NRF series of FPGA Products Data Sheet DS881 GW1NSER series of Bluetooth FPGA Products Data Sheet DS102 GW2A series of FPGA Products Data...

Page 8: ...viations Meaning IP Intellectual Property USB Universal Serial Bus UTMI USB 2 0 Transceiver Macrocell Interface HS High Speed FS Full Speed LS Low Speed NRZI Non Return Zero Inverted 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly by the following ways Webs...

Page 9: ...erview Gowin USB 2 0 SoftPHY IP IP Core Application Supported Devices 1 Arora family LittleBee family excluding GW1N 1 GW1N 1S GW1NZ 1 GW1N 1P5 devices Logic Resource Please refer to Table 2 3 and Table 2 4 Delivered Doc Design Files Verilog encrypted Reference Design Verilog TestBench Verilog Test and Design Flow Synthesis Software GowinSynthesis Application Software Gowin Software V1 9 8 05 and ...

Page 10: ...ll as voltage drops over the cable The USB v2 0 specification sections 7 1 2 and 7 3 2 provides information on current and voltage drop requirements expected to be supplied by a USB Host If the total PCB BOM cannot meet the current and minimum voltage requirements of the specified host the board can be powered with a separate power supply Table 2 2 DC Electrical Characteristics Parameter Symbol Co...

Page 11: ...n GW1NSR 4 and GW2AR 18 series of FPGA ptoducts as an instance the resource utilization is as shown in Table 2 3 and Table 2 4 Table 2 3 Resource Utilization І Device Speed Grade Resource Utilization Notes GW1NSR 4 C7 I6 LUT 384 REG 1109 ALU 13 BSRAM 1 SSRAM 0 IO 7 Table 2 4 Resource Utilization Ⅱ Device Speed Grade Resource Utilization Notes GW2AR 18 C7 I6 LUT 384 REG 1109 ALU 13 BSRAM 1 SSRAM 4 ...

Page 12: ...eceived and then the data transmits to the upper module through UTMI interface In the TX after receiving the data transmitted by UTMI and then going through shift Reg bit stuffer NRZI encoder to generate the serial TX data stream which then is sent to the USB interface via OSER8 Figure 3 1 USB 2 0 SoftPHY Block Diagram IDES8 RX State Machine TX State Machine NRZI Decoder Bit Unstuffer Shift Reg NR...

Page 13: ...term_dp_o usb_term_dn_o 90ohm tracematching As close to FPGA as possible R1 usb_rxdn_i usb_rxdp_i VCC3P3 R6 R7 C1 R1 1 5K ohm R2 0 ohm R3 0 ohm R4 42 ohm R5 42 ohm R6 1 8K ohm R7 75 ohm 1N Series 56 ohm 2A Series C1 1uF R2 R3 R4 R5 Note 1 You can see the followings for the IO port attribute constraints of GW2A series of FPGA usb_dxp_io IO_TYPE LVCMOS33D PULL_MODE NONE DRIVE 4 usb_term_dn_o IO_TYPE...

Page 14: ...ne Bank using adjacent assignment and powering the I O Bank at 3 3V 4 It is required that the adjacent differential pair pins in the same Bank where the usb_dxp_io differential pair is located exist and are not used Taking GW1NSR 4 as an example Figure 3 3 shows the GW1NSR 4 Pinout If the usb_dxp_io differential pair is located at G5 H5 i e IOR11A IOR11B in the diagram it will cause the project to...

Page 15: ...k signal generating fclk_i 5 utmi_data_out_i I 8 Data input 8 bit parallel data transmit bus 6 utmi_txvalid_i I 1 Transmit data valid indicator active high 7 utmi_txready_o O 1 Transmit data ready signal indicating that PHY can receive the data to be transmitted from the controller end 8 utmi_data_in_o O 8 Data output 8 bit parallel data receive bus 9 utmi_rxactive_o O 1 Rx data active indicating ...

Page 16: ...l 2 b00 HS Transfer 2 b01 FS Transfer 2 b10 LS Transfer 2 B11 Reserved 15 utmi_termselect_i I 1 Termination Selection 1 b0 HS termination enable 1 b1 FS LS termination enable 16 usb_dxp_io I O 1 USB data signal Data 17 usb_dxn_io I O 1 USB data signal Data 18 usb_rxdp_i I 1 USB data signal Data input 19 usb_rxdn_i I 1 USB data signal Data input 20 usb_pullup_en_o O 1 1 5K resistor pull up control ...

Page 17: ...pen IP Core Generator After creating the project you can click the Tools tab in the upper left select and open the IP Core Generator via the drop down list as shown in Figure 5 1 Figure 5 1 IP Core Generator 2 Open USB 2 0 SoftPHY IP Core Select Soft IP Core Interface and Interconnect USB 2 0 IP as shown in Figure 5 2 Double click to open the configuration interface ...

Page 18: ...tion Interface Figure 5 3 shows the USB 2 0 SoftPHY IP core configuration interface The ports diagram is on the left of the configuration interface Options are on the right You can configure the file name in File Name You can configure the top module name in Module Name Figure 5 3 USB 2 0 SoftPHY IP Configuration Interface ...

Page 19: ......

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