COMPONENT MAINTENANCE MANUAL
IN 1502H RADAR INDICATOR
TM109102
1-24
May/01
The positive supply voltage (+5V) for U1011 is connected to +VS pin 4 and the
negative supply voltage (-5V) is connected to -VS pin 5. These two voltages are
applied across a band-gap reference circuit internal to U1011 to provide a stable
reference current for the device. Capacitor C1064 connected to pin 2 stabilizes the
control loop and its value determines the bandwidth and recovery time of the
amplifier in the control channel. Pins 12 and 13 (base common) are connected to
ground through diode CR1018. This grounds the bases of internal transistors as
required for proper operation. The small-signal diode (CR1018) improves recovery
time from negative values at the control channel input.
The output of U1011, which is equal to the video input signal multiplied by the
brightness control output of U1017B, is applied to the inverting input (pin 2) of
buffer amplifier U1007. The non-inverting input of U1007 is biased negative to
shift the output below ground so it can be properly handled by the next stage of
amplification.
The BIAS potentiometer, R1050, is adjusted to eliminate the background retrace
lines from the CRT display. The GAIN CTL potentiometer (R1052) is adjusted to
set the gain to obtain the correct level of the video signal at TP1017.
The final stage of amplification is formed by Q1018, Q1021, Q1022, and
associated components. This circuit comprises an inverting amplifier which has a
gain of approximately 12. The video signal from U1007 is applied to the emitter of
transistor Q1018.
Supply voltage (Vcc) for the stage is +65 volts (-0501) or +53 volts (-0503, -0504),
which is used by complementary transistor pair Q1021/QI022 to develop the
output signal. When the BRT control is set to maximum, this video swings from a
minimum of about +4 volts (CRT gun fully on) to +45 volts (fully off).
(d) Sync Separator and Blanking Circuits
The output from U1001 is coupled through C1091 to input pin 2 of video sync
separator U1005. This integrated circuit extracts timing information, including
composite and vertical sync, from negative-going RS-170 or CCIR video input
signals with amplitude from 0.5 to 2.0 volts peak-to-peak. The vertical output is
produced on the rising edge of the first serration in the vertical sync period. See
timing diagram provided with the integrated circuit diagram for this device in
section III of this manual.
The leading (negative-going) edge of the composite sync output at pin 1 of U1005
triggers single-shot multivibrator U1006B, which generates negative 2.5
microsecond pulses at pin 9 in response. These pulses are applied to the sync
input of TV horizontal processor device U1021, discussed next. They are also
gated through U1016B to the DC restorer circuit, which restores the DC
The document reference is online, please check the correspondence between the online documentation and the printed version.
