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CONFIDENTIAL 7

페이지

2005-06-08

3. EXTERNAL INTERFACES

3.1 System connector

z

RF Input

A

z

GPIO[0..15] GPIO-lines

I/O

z

UART ports PORT0 and PORT1 UART ports I/O

z

XRESET External reset (active low)

I

z

Supply

voltage

S

z

V_ANTENNA External antenna bias

S

HPM103H-6

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Summary of Contents for HPM103H-6

Page 1: ...CONFIDENTIAL 1 페이지 2005 06 08 GPS Engine Module HPM103H 6 GPS Receiver REV 1 10 HPM103H 6 ...

Page 2: ...diagram 4 2 MECHANICAL SPECIFICATION 5 2 1 Pictures 5 2 2 Pin Configuration 6 3 EXTERNAL INTERFACES 7 3 1 System connector 7 3 2 Reset 10 3 3 UART interface 10 3 4 GPIO interface 11 3 5 RF interface 12 3 6 Interfacing considerations 13 4 APPLICATION NOTES FOR HPM103H 6 15 4 1 External Interfaces 15 4 2 Antenna issues 15 4 3 Application Circuit 17 HPM103H 6 ...

Page 3: ...ssor based on uN8031 chip z Dual UART 3V CMOS levels for serial data z SPI interface option z 16 bit GPIO interface z 32768Hz RTC z 16Mbit FLASH memory 1024k x 16bit The receiver needs only the following external inputs z Regulated 2 7 3 3V supply z Active GPS antenna bias supply if needed z External reset input z GPS Antenna signal passive or active antenna 1 2 Physical specification z Size 25 4 ...

Page 4: ...3 0 V z TTFF Hot Start 8 6 sec typ Warm Start 38 sec typ Cold Start 53 sec typ z Sensitivity 138 dBm Acquisition 150 5 dBm Navigation 152 dBm Tracking z Power Consumption Navigating 130mW 2 7V ave Idle mode Navigation stopped 22mW 2 7V typ Sleep mode 120µW 2 7V typ RTC Back Up mode 1 5 uA max z Protocols NMEA 0183 V3 0 proprietary iTALK binary protocol 1 4 Block diagram Figure 1 Block diagram of H...

Page 5: ...CONFIDENTIAL 5 페이지 2005 06 08 2 MECHANICAL SPECIFICATION Pictures 2 1 Pictures Figure 2 HPM103H 6 modules w shield Figure 3 HPM103H 6 Top view w o shield HPM103H 6 ...

Page 6: ...CONFIDENTIAL 6 페이지 2005 06 08 2 2 HPM103H 6 Pin Configurations Figure 4 Pin Configuration HPM103H 6 ...

Page 7: ...8 3 EXTERNAL INTERFACES 3 1 System connector z RF Input A z GPIO 0 15 GPIO lines I O z UART ports PORT0 and PORT1 UART ports I O z XRESET External reset active low I z Supply voltage S z V_ANTENNA External antenna bias S HPM103H 6 ...

Page 8: ...signal ground 16 GND Power and signal ground 17 RF Input RF input 50 ohm 18 GND Power and signal ground 19 V_ANTENNA Input Leave unconnected if not used 20 VCC_RF Output Can be used as power supply for an active antenna 21 V_Bat Input Backup voltage supply for RTC 22 XRESET Input Active low reset 4 23 GPIO10 I O General Purpose I O 1 24 GPIO6 I O General Purpose I O 1 25 GPIO5 I O General Purpose ...

Page 9: ...VIL max 0 3 x VCC The base band processor uN8031 includes also a keeper and the drive impedance should be less than 10kohm in order to change the state 3 The base band processor uN8031 includes an internal 100k pull up resistor to VCC no keeper VIH min 0 7 x VCC VIL max 0 3 x VCC 4 HPM103H 6 module contains internal 10k pull up resistor to VCC VIH min 0 7 x VCC VIL max 0 3 x VCC 5 The base band pr...

Page 10: ...ce Two asynchronous UART ports are available for serial interfacing The baud rates are fully programmable The data format is however fixed x N 8 1 i e x baud No parity eight data bits and 1 stop bit No other data formats are supported LSB is sent first CMOS signal levels are used Parity N Data Bits 8 Stop bits 1 Figure 7 UART Data format The UART ports are named PORT0 and PORT1 PORT0 is used e g f...

Page 11: ...rs R12 and R13 at GPIO14 15 Other boot modes can be selected with external drive at the system connector i e in Evaluation Kit or by external host at GPIO14 15 One of the GPIO lines GPIO13 is reserved for active power control of the internal LNA and it can be also used for controlling external LNA Also GPIO12 is reserved internally for controlling the flash memory GPIO11 is reserved for external W...

Page 12: ...xample layout Figure 8 Example of RF interface layout on customer PCB The width of the 50ohm stripline is dependent of the PCB material and thickness On FR4 material the width W at 1 5GHz is roughly 2 times the thickness H of the PCB If the PCB thickness is for example 0 8mm then the width of the stripline should be 1 6mm and so on W H GND plane on lower PCB layer Figure 9 Stripline widths versus ...

Page 13: ...he RF input 3 6 Interfacing considerations The following recommendations should be taken into account when interfacing to the HPM103H 6 GPS receiver z The HPM103H 6 can be used with passive antennas if the cable loss is below 1 dB Otherwise an active antenna is needed to compensate for the cable loss Net gain from the active antenna prior HPM103H 6 should be between 6 and 32 dB z Use a solid GND p...

Page 14: ...e front end Blocking level is about 2 dBm at the RF input S N degradation 3 dB The receiver has a zero IF topology If two receivers are connected to the same antenna the local oscillator leakage may cause blocking Use a power combiner splitter that gives at least 20 dB isolation between ports HPM103H 6 ...

Page 15: ...ul interfaces z Boot Mode Select using GPIO15 dedicated GPIO pin z Control of external antenna bias through GPIO13 dedicated GPIO pin z External Wake up control using GPIO11 dedicated GPIO pin Rest of the I O is also available for customer applications 4 2 Antenna issues The HPM103H 6 GPS receiver can be used with a passive antenna One typical application is shown below where the GPS antenna and t...

Page 16: ...haracteristics declines causing polarization miss match loss reduction in signal levels and reduction in multi path mitigation navigation accuracy These all issues affect the radiation pattern and the resonance frequency of the antenna The antenna selection and design is a very critical issue and must be reviewed case by case Note also that the enclosure material e g plastic cover also affect the ...

Page 17: ...CONFIDENTIAL 17 페이지 2005 06 08 4 3 Application Circuit HPM103H 6 ...

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