- 32 -
MPUCS0N
MD19
1
P_17
PWM
33RX4 TO 100RX4
MA6
MD1
R1
1K5
I2C Address:
7C/7D
Not
Populated
42PDP TV_MAIN
C-03
SVP-EX 1 of 2
Qingdao Haier Electronics Co.,Ltd.
B
9
30
Saturday, February 18, 2006
Title
Size
Document Number
Rev
Date:
Sheet
of
A3
R4
0R_DNS
P_39
MD4
1
ALE
DQS0
SVP-EX [256]
(1 of 2)
U1A
SVP-EX_256
73
75
76
78
84
86
88
90
91
93
94
96
102
104
106
108
148
150
152
154
160
162
163
165
166
168
170
172
178
180
181
183
79
97
159
177
82
100
156
174
109
111
112
114
115
117
118
120
122
123
125
126
130
131
133
135
137
138
140
142
144
145
147
193
191
139
141
179
171
161
153
136
134
124
119
103
95
85
77
173
169
155
151
132
129
121
116
105
101
87
83
81
80
13
12
15
16
14
203
202
201
200
197
196
195
194
216
217
218
219
220
18
17
98
99
157
158
176
175
190
189
188
192
206
207
208
209
210
211
212
213
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM0
DQM1
DQM2
DQM3
DQ
S0
DQ
S1
DQ
S2
DQ
S3
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
MCK0
MCK0#
CS0#
CS1#
RAS#
CAS#
MVREF
WE#
CLKE
BA0
BA1
MPUGPIO0
MPUGPIO1
VDDR
VSSR
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VDDM
VSSM
RESET
TESTMODE
V5SF
SDA
SCL
A_D7
A_D6
A_D5
A_D4
A_D3
A_D2
A_D1
A_D0
RD#
WR#
ALE
MPUCS0N
INT#
FLD/IO
P_17
VSSM
VDDM
VDDM
VSSM
VSSM
VDDM
MPUGPIO2
MPUGPIO3
MPUGPIO4
NC
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
CS0#
C315
100nF
A6
R8
0R_DNS
DQ
S0
I2C Address:
7E/7F
MPUGPIO2
33RX4 TO 100RX4
MD18
VD3_3
5V-1_CPU
DQS[0..3]
BA0
P_17
R16
1K
MPU has
Data/Address
multiplex
MPUGPIO1
MPUGPIO4
1
AD1
RD_EX
C319
100nF
MD[0..31]
MD5
MPUCS0N
VCC
MA2
A2
R6
10R
C306
100nF
C3
100pF
INPUT
MPUGPIO1
MD17
AD4
TP1
TP_T_C30
C6
100nF
RP43
100Rx
4
1
2
3
4
8
7
6
5
3V_SDA
DQM0
MPUGPIO3
C313
100nF
MPUGPIO0
R20
10K_DNS
C305
100nF
1
MA4
SDA_EX
1
C307
100nF
TP5
TP_T_C30
MPUGPIO0
MD11
MD20
TP3
TP_T_C30
RP42
100Rx
4
1
2
3
4
8
7
6
5
OUTPUT
MD13
MD27
MPUGPIO2
MD3
MD22
1
E_PWM
C2
100nF
0
1
MVREF
WE#
MA11
AD0
Test pads for DDR
CAS#
TP24
TP_T_C30
DQM1
MD30
Q1
MMBT3904
1
2
3
VDDMQ
BRT_CNTL
C309
100nF
R13
4K7
MD14
1
MPUGPIO0
TP2
TP_T_C30
1
MD0
RP1
100Rx4
1
2
3
4
8
7
6
5
R5
4K7
*CS1N
VDDMQ
SDA_EX
MPUCS0N
MD21
MCLK0#
R10
68R
P_17
WR
DQM[0..3]
BA1
MA8
0
VDDH3_3
A[0..7]
FIELD
DQM0
Connector for Amtel AT76C112 Video Output
if not a test pad, an enlarged via
underneath the chip or exposed
trace. Possible DQS MCLK
exposed trace, DQ enlarged via
MA10
MPUGPIO1
R15
10K_DNS
1
C311
100nF
0
VDDM
DQM2
MD23
AD5
0
C5
68pF
R3
0R_DNS
0
1
MD25
TP4
TP_T_C30
C317
100nF
MD16
MPUGPIO0
GPIO
SCL_EX
DQ
S3
MD9
R7
10K
AD[0..7]
0
MCLK0
MD31
MD24
MD0
MPU has
separated
Address/Data
1
MA1
RP2
100Rx4
1
2
3
4
8
7
6
5
0
INT#
AD2
R18
10K
MA[0..11]
MD6
R19
10K_DNS
0
TP6
TP_T_C30
MPUGPIO4
MD12
1
RAS#
A5
C320
100nF
MD15
TP25
TP_T_C30
MPUGPIO0
RST_SVP
AD7
MD26
VDDH3_3
CLKE
MA3
C4
68pF
MD7
A0
C308
100nF
C312
100nF
1
MA5
AD3
MD10
R9
68R
MD8
C318
100nF
MD2
C316
100nF
3V_SCL
DQ
S2
*CS1N is not a input or output pin
CS1N=0: SVP-EX CPU access enabled
CS1N=1:SVP-EX CPU access disabled
VDDH3_3
A1
1
R21
1K
VDDMQ
MCLK0
CS
R2
4K7
MA7
AD6
MD28
A7
For EX52 to use
this table
1
MD29
DQM3
SCL_EX
C314
100nF
A4
C310
100nF
MCLK0#
MA9
+
C1
10uF/16V
R12
10K
MPUGPIO3
DQ
S1
MA0
R17
0R
Summary of Contents for P42LV6-T1
Page 1: ... 1 P42LV6 T1 ...
Page 8: ... 8 Printed Circuit Digital Board Main Board Printed Circuit Emulation board ...
Page 9: ... 9 4 Panel part a Adjustment ...
Page 10: ... 10 ...
Page 11: ... 11 b Trouble shooting ...
Page 12: ... 12 ...
Page 13: ... 13 ...
Page 14: ... 14 ...
Page 15: ... 15 ...
Page 16: ... 16 ...
Page 17: ... 17 ...
Page 18: ... 18 ...
Page 19: ... 19 ...
Page 20: ... 20 ...
Page 22: ... 22 3 PSU ON OFF sequence ...
Page 23: ... 23 4 PSU INPUT OUTPUT PIN ...