Hal Communications DKB-2010 Instruction Manual Download

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"end" bit is used by the Morse character generator to produce a space between characters, as explained in
Section 4.12.

In the RTTY mode, data bits are clocked out of the shift register at a constant rate, as all select pulses

are of the same duration, In Morse operation, however, the dashes are three times as long as the dots. The

register clock rate therefore depends on the code pattern. The clock pulse is supplied by the Morse
character generator rather than a fixed clock oscillator. The output of the character generator is inverted

and fed to the shift register clock bus via the

MORSE SHIFT

line. A shift occurs at the end of each dot or

dash, shifting the data bit for the next code pulse to the register output, from which it passes to the

character generator.

4.9 RTTY Encoder and Loop Interface

The serial output data bits from the shift register are coupled to both the RTTY encoder (Figure 8.7) and

the Morse character generator. With the keyboard in the RTTY mode, the Morse circuit is disabled and the
output bits activate only the RTTY loop keying circuitry.

The RTTY encoder accepts data inputs from three sources: the shift register output, the case character

generator, and the BREAK key circuit. Control inputs are received from the case change flip-flop, the case
insert flip-flop, and the M/R bus.

The Loop circuit is keyed by an NPN transistor, Q2, which is isolated from ground and the power supply

bus by a transformer in its base circuit. During mark pulses, the VHØ clock signal passes through a NAND
gate (IC-34) and an inverter (IC-24) to drive the emitter of a current source, transistor Q1. The pulses are
coupled through transformer T1 to a half-wave rectifier circuit, the output of which drives the keying
transistor into conduction. During space pulses, the VHØ clock signal is prevented from reaching the keying

circuit by a low level at pin 9 or 11 of IC-34.

During normal operation when a case change is not required, the gate is controlled by the output of the

shift register, which is applied to one input of a NAND gate (pin 9 of IC-33). With the case change circuitry
inactive, pin 11 of the gate is held high. The

M/R

bus is also high, holding pin 10 high. The shift register

signal therefore appears inverted at the gate output. When the register output is high the gate output is

low. This signal, fed to pin 11 of IC-34, cuts off the flow of VHØ clock pulses to the keying circuit and loop
current is prevented from flowing. Conversely, when the register output is low, the gate output is high and,
assuming that the BREAK line is low (BREAK key released), clock pulses flow and the keying transistor
conducts.

The BREAK key is provided to manually interrupt the loop circuit, When the keyswitch is closed, the

BREAK line is high. Fed to the input of a NAND gate (part of IC-55), it is combined with a signal from the

M/R

bus, which is high when the keyboard is in the RTTY mode. With the BREAK line high, the gate output

is forced low, preventing clock pulses from reaching the keying circuit. The loop current is therefore
interrupted until the key is released.