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IMAGETEAM™ 4X00 Series Integration Manual
IT4X00 Series Register Settings for the PXA27XI
Register settings for the PXA27X CSI interface for use with the IT4X00 Series engines are shown in the following table.
Notes:
d
Dynamic value that changes as needed for image capture control.
DMA_EN
DMA request Enable. 0=disable; 1=enable.
ENB
Camera interface Enable. 0=disable; 1=enable.
DIS
Camera interface Disable. 0=do not disable camera interface after capture (continuous scanning); 1=disable cam-
era interface after capture is complete. See CISR CDD flag.
TOM
Time-Out Mask. 0=Generate time-out condition interrupt; 1=Do not generate time-out condition interrupt (time-out
of stalled image capture).
QDM
Quick Disable Mask. 0=Generate QD interrupt; 1=Do not generate QD interrupt.
CDM
Disable Done Mask. 0=Generate capture interface disable done interrupt; 1=Do not generate capture interface dis-
able done interrupt.
EOFM
End of Frame Mask. 0=Generate an interrupt at end of frame; 1=Do not generate EOF interrupt.
Notes:
PPL
Pixels Per Line. Value of 0 to 2047 where actual number of imager pixels per line = PPL+1 (PPL = imager pixels per
line-1).
RAW_BPP Raw Bits Per Pixel. 0b00=8; 0b01=9; 0b10=10; 0b11=reserved.
DW
Imager Data Width. 0b000=4; 0b001=5; 0b010=8; 0b100=10.
Register
Hex
Address
Initial Hand Held
Products
Hex Dec
Timing Control
02, 01
001D
-
Frame Width (pclk)
0D, 0C
035A
858
Frame Height (lines)
0F, 0E
020D
525
Beg act pix out (pclk)
11,10
00B4
180
Beg act frame out (lines)
15, 14
0209
521
Horiz pulse width (pclk)
19, 18
0040
64
Vert Pulse Width (lines)
1B, 1A
01E0
480
CDS subt pulse pos (pclk)
Must be FW - 1 or placed after last active pixel
9C, 9B
0342
834
Exp time (pclk)
1D, 1C
FF00
65280
CICR0 - Capture Interface Control Register 0
bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Setting
d
0
0
d
d
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
d
1
1
1
1
d
d
0
d
1
DMA_EN
PA
R
_
E
N
SL_CAP_EN
EN
B
DIS
SIM
Reserved
TO
M
RD
V
A
M
FEM
EOL
M
PERRM
QDM
CDM
SOFM
EOFM
FOM
CICR1 - Capture Interface Control Register 1
bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Setting
X
0
0
X
X
X
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
TBIT
RGBT_CONV
Reser
v
ed
PPL (Pixels Per Line)
RGB_CONV
RGB_F
YCBR_F
RGB_
BPP
RA
W_BPP
COLOR_SP
DW
Summary of Contents for IMAGETEAM IT4000HD
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