12.3 Pin Definitions
FILT1 — Phase-Locked Loop Filter
Connects to an external filter for the on-chip phase-locked loop.
FILT2 — Phase Locked Loop Filter
Connects to an external filter for the on-chip phase-locked loop.
CLKIN, XTALI — External Clock Input/Crystal Oscillator Input
CS49400 clock input. This pin accepts an external clock input signal that is used to drive the
internal core logic. When in internal clock mode (CLKSEL == VSS), this input is connected to
the internal PLL from which all internal clocks are derived. When in external clock mode
(CLKSEL == VDD), this input is connected to the DSP clock. Alternatively, a 12.288 mhZ
crystal oscillator can be connected between XTALI and XTALO.
INPUT
XTALO — Crystal Oscillator Output
Crystal oscillator output.
OUTPUT
CLKSEL — DSP Clock Select
This pin selects the internal source clock. When CLKSEL is low, CLKIN is connected to the
internal PLL from which all internal clocks are derived. When CLKSEL is high, the PLL is
bypassed and the external clock directly drives all input logic.
INPUT
FDAT7 — DSPAB Bidirectional Data Bus
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
In parallel host mode, these pins provide a bidirectional data bus to DSPAB. These pins have
an internal pull-up.
BIDIRECTIONAL - Default: INPUT
FA0, FSCCLK — Host Parallel Address Bit Zero or Serial Control Port Clock
In parallel host mode, this pin serves as one of two address input pins used to select one of
four parallel registers. In serial host mode, this pin serves as the serial control clock signal,
specifically as the SPI clock input.
INPUT
AVR340
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