- 27 -
No.
Pin Name
I/O
FUNCTION
22
CMODE
I
Master Clock Selection pin
"L": MCLK=256fs
"H": MCLK=384fs
23
SMODE1
I
Serial Interface Mode Select pin
15
SMODE2
I
Defines the directions of LRCK, SCLK and FSYNC pins and
Output Data Format. SMODE2 is pull-down pin.
SMODE1
SMODE2
MODE
LRCK
L
L Slave mode: MSB justified:
:H/L
H
L
Master mode: Similar to I
2
S
:H/L
L
H Slavemode:I
2
S
:L/H
H
H
Master mode:I
2
S
:L/H
24
VB
---
Substrate Power Supply, +5V
9. 74VHC374
➀
Logic Symbol
➁
Connection Diagram
➂
Pin Descriptions
Pin Names
Description
D
0
-
D
7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O
0
-
O
7
3-STATE Outputs
Summary of Contents for CDR 2
Page 13: ... 13 BLOCK DIAGRAM 1 AK8563 Block Diagram ...
Page 18: ... 18 5 MN12511 Block Diagram D15 D0 NSDO VDD VSS VPP NCE NSCK NSDI CK CK OE OK R R OK ...
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Page 55: ... 58 ASIC IC 301 74 105 107 BITSTR 1 IC 301 80 86 88 107 105 74 80 86 88 ...
Page 56: ... 59 U COM IC 202 12 14 16 12 14 16 ...
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Page 76: ... 69 PCB LAYOUT CD PLAY TOP SECTION ...
Page 77: ... 70 CD PLAY BOTTOM SECTION ...
Page 78: ... 71 CD RECORD TOP SECTION CD RECORD BOTTOM SECTION ...
Page 79: ... 72 AUDIO TOP SECTION AUDIO BOTTOM SECTION ...
Page 80: ... 73 FRONT SECTION ...
Page 81: ... 74 POWER SECTION ...
Page 82: ... 75 BLOCK DIAGRAM CD RECORD SECTION ...
Page 83: ... 76 CD PLAY SECTION ...
Page 85: ... 78 WIRING DIAGRAM ...